diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py
index af4bfa9..5cb54e5 100755
--- a/litex_boards/targets/aller.py
+++ b/litex_boards/targets/aller.py
@@ -116,7 +116,7 @@ class PCIeSoC(SoCCore):
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
+        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
             data_width = 64,
             bar0_size  = 0x20000)
         self.pcie_phy.add_timing_constraints(platform)
diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py
index 3672abb..8ffe98c 100755
--- a/litex_boards/targets/nereid.py
+++ b/litex_boards/targets/nereid.py
@@ -114,7 +114,7 @@ class PCIeSoC(SoCCore):
 
         # PCIe -------------------------------------------------------------------------------------
         # PHY
-        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"),
+        self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
             data_width = 64,
             bar0_size  = 0x20000)
         self.pcie_phy.add_timing_constraints(platform)