From 27c242b2ca204a009595b03b75223ded35de04cc Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 7 May 2020 12:18:39 +0200 Subject: [PATCH] targets/pcie: switch to PCIe X4 on all boards that support it. --- litex_boards/targets/aller.py | 2 +- litex_boards/targets/nereid.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index af4bfa9..5cb54e5 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -116,7 +116,7 @@ class PCIeSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- # PHY - self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 64, bar0_size = 0x20000) self.pcie_phy.add_timing_constraints(platform) diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 3672abb..8ffe98c 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -114,7 +114,7 @@ class PCIeSoC(SoCCore): # PCIe ------------------------------------------------------------------------------------- # PHY - self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1"), + self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"), data_width = 64, bar0_size = 0x20000) self.pcie_phy.add_timing_constraints(platform)