From 27dce96bf854acdf1e8ba6245c5db6dc3393399c Mon Sep 17 00:00:00 2001 From: Gwenhael Goavec-Merou Date: Fri, 29 Mar 2024 07:16:46 +0100 Subject: [PATCH] targets/xilinx_zc706: SFP/etherbone working: added a note to use it --- litex_boards/targets/xilinx_zc706.py | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/litex_boards/targets/xilinx_zc706.py b/litex_boards/targets/xilinx_zc706.py index 1c3fe02..c46db4b 100755 --- a/litex_boards/targets/xilinx_zc706.py +++ b/litex_boards/targets/xilinx_zc706.py @@ -7,6 +7,17 @@ # SPDX-License-Identifier: BSD-2-Clause # Build/use +# Build/Load bitstream: +# ./xilinx_zc7006.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load +# +# Test Ethernet: +# ping 192.168.1.50 +# +# Test Console: +# litex_server --udp +# litex_term crossover +# +# # Build/Load bitstream: # ./xilinx_zc706.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load # @@ -79,8 +90,11 @@ class BaseSoC(SoCCore): with_pcie = False, **kwargs): platform = xilinx_zc706.Platform() + + # When nor jtagbone, nor etherbone are set forces jtagbone. kwargs["uart_name"] = "crossover" - kwargs["with_jtagbone"] = True + if kwargs["with_jtagbone"] or with_etherbone: + kwargs["with_jtagbone"] = True # CRG -------------------------------------------------------------------------------------- self.crg = _CRG(platform, sys_clk_freq)