targets/xilinx_zc706: SFP/etherbone working: added a note to use it

This commit is contained in:
Gwenhael Goavec-Merou 2024-03-29 07:16:46 +01:00
parent 917ae33351
commit 27dce96bf8
1 changed files with 15 additions and 1 deletions

View File

@ -7,6 +7,17 @@
# SPDX-License-Identifier: BSD-2-Clause # SPDX-License-Identifier: BSD-2-Clause
# Build/use # Build/use
# Build/Load bitstream:
# ./xilinx_zc7006.py --with-etherbone --uart-name=crossover --csr-csv=csr.csv --build --load
#
# Test Ethernet:
# ping 192.168.1.50
#
# Test Console:
# litex_server --udp
# litex_term crossover
#
#
# Build/Load bitstream: # Build/Load bitstream:
# ./xilinx_zc706.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load # ./xilinx_zc706.py --with-jtagbone --uart-name=crossover --csr-csv=csr.csv --build --load
# #
@ -79,8 +90,11 @@ class BaseSoC(SoCCore):
with_pcie = False, with_pcie = False,
**kwargs): **kwargs):
platform = xilinx_zc706.Platform() platform = xilinx_zc706.Platform()
# When nor jtagbone, nor etherbone are set forces jtagbone.
kwargs["uart_name"] = "crossover" kwargs["uart_name"] = "crossover"
kwargs["with_jtagbone"] = True if kwargs["with_jtagbone"] or with_etherbone:
kwargs["with_jtagbone"] = True
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq)