From 28a6fad7056b8034fd0e4e3b2ac0102def6f726e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 4 Jan 2022 11:25:18 +0100 Subject: [PATCH] targets/efinix_titanium_ti60_f225: Defaults to 200MHz clock and increase HyperRam size to 32MB. --- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 563c6d6..4cdd27e 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -47,7 +47,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(50e6), with_spi_flash=False, with_hyperram=False, **kwargs): + def __init__(self, sys_clk_freq=int(200e6), with_spi_flash=False, with_hyperram=False, **kwargs): platform = efinix_titanium_ti60_f225_dev_kit.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -68,7 +68,7 @@ class BaseSoC(SoCCore): if with_hyperram: self.submodules.hyperram = HyperRAM(platform.request("hyperram"), latency=7) - self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=16*1024*1024)) + self.bus.add_slave("main_ram", slave=self.hyperram.bus, region=SoCRegion(origin=0x40000000, size=32*1024*1024)) # Build -------------------------------------------------------------------------------------------- @@ -77,7 +77,7 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") - parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default: 50MHz)") + parser.add_argument("--sys-clk-freq", default=200e6, help="System clock frequency (default: 200MHz)") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") parser.add_argument("--with-hyperram", action="store_true", help="Enable HyperRAM") builder_args(parser)