From 296c99f06538f42f839bbcd949ae3d7d34bf15c8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 14 Jan 2022 09:39:42 +0100 Subject: [PATCH] digilent_pynq_z1: Do minor cosmetic cleanups. --- litex_boards/platforms/digilent_pynq_z1.py | 83 +++++++++++----------- litex_boards/targets/digilent_pynq_z1.py | 26 +++---- 2 files changed, 54 insertions(+), 55 deletions(-) mode change 100644 => 100755 litex_boards/targets/digilent_pynq_z1.py diff --git a/litex_boards/platforms/digilent_pynq_z1.py b/litex_boards/platforms/digilent_pynq_z1.py index 558e3ee..ffaa153 100644 --- a/litex_boards/platforms/digilent_pynq_z1.py +++ b/litex_boards/platforms/digilent_pynq_z1.py @@ -35,7 +35,7 @@ _io = [ ("user_btn", 2, Pins("L20"), IOStandard("LVCMOS33")), ("user_btn", 3, Pins("L19"), IOStandard("LVCMOS33")), - #Serial + # Serial ("serial", 0, Subsignal("tx", Pins("pmoda:0")), Subsignal("rx", Pins("pmoda:1")), @@ -44,9 +44,9 @@ _io = [ # Audio ("aud_pwm", 0, Pins("R18"), IOStandard("LVCMOS33")), - ("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")), - ("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")), - ("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")), + ("aud_sd", 0, Pins("T17"), IOStandard("LVCMOS33")), + ("m_clk", 0, Pins("F17"), IOStandard("LVCMOS33")), + ("m_data", 0, Pins("G18"), IOStandard("LVCMOS33")), # Chipkit Single Ended Analog Input ("ck_an_n", 0, Pins("D18"), IOStandard("LVCMOS33")), @@ -65,16 +65,15 @@ _io = [ # Chipkit SPI ("ck_miso", 0, Pins("W15"), IOStandard("LVCMOS33")), ("ck_mosi", 0, Pins("T12"), IOStandard("LVCMOS33")), - ("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")), - ("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")), + ("ck_sck", 0, Pins("H15"), IOStandard("LVCMOS33")), + ("ck_ss", 0, Pins("F16"), IOStandard("LVCMOS33")), # Chipkit I2C ("ck_scl", 0, Pins("P16"), IOStandard("LVCMOS33")), ("ck_sda", 0, Pins("P15"), IOStandard("LVCMOS33")), # Crypto SDA - ("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")) - + ("crypto_sda", 0, Pins("J15"), IOStandard("LVCMOS33")), ] _ps7_io = [ @@ -83,13 +82,13 @@ _ps7_io = [ ("ps7_porb", 0, Pins("C7")), ("ps7_srstb", 0, Pins("B10")), ("ps7_mio", 0, Pins( - "E6 A7 B8 D6 B7 A6 A5 D8", - "D5 B5 E9 C6 D9 E8 C5 C8", + " E6 A7 B8 D6 B7 A6 A5 D8", + " D5 B5 E9 C6 D9 E8 C5 C8", "A19 E14 B18 D10 A17 F14 B17 D11", "A16 F15 A15 D13 C16 C13 C15 E16", "A14 D15 A12 F12 A11 A10 E13 C18" - "D14 C17 E12 A9 F13 B15 D16 B14" - "B12 C12 B13 B9 C10 C11")), + "D14 C17 E12 A9 F13 B15 D16 B14" + "B12 C12 B13 B9 C10 C11")), ("ps7_ddram", 0, Subsignal("addr", Pins( "N2 K2 M3 K3 M4 L1 L4 K4", @@ -102,10 +101,10 @@ _ps7_io = [ Subsignal("cs_n", Pins("N1")), Subsignal("dm", Pins("A1 F1 T1 Y1")), Subsignal("dq", Pins( - " C3 B3 A2 A4 D3 D1 C1 E1", - " E2 E3 G3 H3 J3 H2 H1 J1", - " P1 P3 R3 R1 T4 U4 U2 U3", - " V1 Y3 W1 Y4 Y2 W3 V2 V3"), + "C3 B3 A2 A4 D3 D1 C1 E1", + "E2 E3 G3 H3 J3 H2 H1 J1", + "P1 P3 R3 R1 T4 U4 U2 U3", + "V1 Y3 W1 Y4 Y2 W3 V2 V3"), ), Subsignal("dqs_n", Pins("B2 F2 T2 W4")), Subsignal("dqs_p", Pins("C2 G2 R2 W5")), @@ -120,37 +119,37 @@ _ps7_io = [ _hdmi_rx_io = [ # HDMI Rx - ("hdmi_rx", 0, - Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")), - Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")), - Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")), - Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")), + ("hdmi_rx", 0, + Subsignal("cec", Pins("H17"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("N18"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("P19"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("V20"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("W20"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("T20"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("U20"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("N20"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("P20"), IOStandard("TMDS_33")), + Subsignal("hpd", Pins("T19"), IOStandard("LVCMOS33")), + Subsignal("scl", Pins("U14"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("U15"), IOStandard("LVCMOS33")), ), ] _hdmi_tx_io = [ # HDMI Tx - ("hdmi_tx", 0, - Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")), - Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")), - Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")), - Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")), - Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")), - Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")), - Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")), - Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")), - Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")), - Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")), - Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")), - Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")), + ("hdmi_tx", 0, + Subsignal("cec", Pins("G15"), IOStandard("LVCMOS33")), + Subsignal("clk_p", Pins("L16"), IOStandard("TMDS_33")), + Subsignal("clk_n", Pins("L17"), IOStandard("TMDS_33")), + Subsignal("data0_p", Pins("K17"), IOStandard("TMDS_33")), + Subsignal("data0_n", Pins("K18"), IOStandard("TMDS_33")), + Subsignal("data1_p", Pins("K19"), IOStandard("TMDS_33")), + Subsignal("data1_n", Pins("J19"), IOStandard("TMDS_33")), + Subsignal("data2_p", Pins("J18"), IOStandard("TMDS_33")), + Subsignal("data2_n", Pins("H18"), IOStandard("TMDS_33")), + Subsignal("hpdn", Pins("R19"), IOStandard("LVCMOS33")), + Subsignal("scl", Pins("M17"), IOStandard("LVCMOS33")), + Subsignal("sda", Pins("M18"), IOStandard("LVCMOS33")), ), ] diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py old mode 100644 new mode 100755 index add8416..dde16e7 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -28,16 +28,16 @@ from litex.soc.cores.led import LedChaser class _CRG(Module): def __init__(self, platform, sys_clk_freq, toolchain, use_ps7_clk=False, with_video_pll=False): self.rst = Signal() - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_hdmi = ClockDomain() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_hdmi = ClockDomain() self.clock_domains.cd_hdmi5x = ClockDomain() # # # - # Clk + # Clk clk125 = platform.request("sysclk") - # PLL + # PLL if use_ps7_clk: assert sys_clk_freq == 125e6 self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) @@ -49,7 +49,7 @@ class _CRG(Module): pll.create_clkout(self.cd_sys, sys_clk_freq) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. - # Video PLL. + # Video PLL. if with_video_pll: self.submodules.video_pll = video_pll = S7MMCM(speedgrade=-1) video_pll.reset.eq(self.rst) @@ -89,7 +89,7 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = _CRG(platform, sys_clk_freq, toolchain, with_video_pll=with_video_terminal) - # Video ------------------------------------------------------------------------------------ + # Video ------------------------------------------------------------------------------------ if with_video_terminal: self.submodules.videophy = VideoS7HDMIPHY(platform.request("hdmi_tx"), clock_domain="hdmi") self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi") @@ -104,10 +104,10 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on PYNQ Z1") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency (default: 125MHz)") - parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)") + parser.add_argument("--build", action="store_true", help="Build bitstream.") + parser.add_argument("--load", action="store_true", help="Load bitstream.") + parser.add_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") + parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") builder_args(parser) soc_core_args(parser) @@ -115,9 +115,9 @@ def main(): args = parser.parse_args() soc = BaseSoC( - sys_clk_freq = int(float(args.sys_clk_freq)), - with_video_terminal = args.with_video_terminal, - **soc_core_argdict(args) + sys_clk_freq = int(float(args.sys_clk_freq)), + with_video_terminal = args.with_video_terminal, + **soc_core_argdict(args) ) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args), run=args.build)