From 2a0fbcadd224ad102463c4c0b04f2bd8b3c74407 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 6 Nov 2019 09:29:55 +0100 Subject: [PATCH] ac701: add pcie_x1 pins --- litex_boards/community/platforms/ac701.py | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/litex_boards/community/platforms/ac701.py b/litex_boards/community/platforms/ac701.py index 1e731aa..4424bdf 100644 --- a/litex_boards/community/platforms/ac701.py +++ b/litex_boards/community/platforms/ac701.py @@ -83,6 +83,16 @@ _io = [ Subsignal("reset_n", Pins("N8"), IOStandard("LVCMOS15")) ), + ("pcie_x1", 0, + Subsignal("rst_n", Pins("M20"), IOStandard("LVCMOS25")), + Subsignal("clk_p", Pins("F11")), + Subsignal("clk_n", Pins("E11")), + Subsignal("rx_p", Pins("D12")), + Subsignal("rx_n", Pins("C12")), + Subsignal("tx_p", Pins("D10")), + Subsignal("tx_n", Pins("C10")) + ), + ("vadj_on_b", 0, Pins("R16"), IOStandard("LVCMOS25")), ("gtp_refclk", 0,