diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 3443c91..efd8a9f 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -29,7 +29,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index 1390a47..a173884 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -31,7 +31,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.stop = Signal() @@ -70,8 +70,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index 86b1d78..a50853f 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -38,7 +38,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -74,8 +74,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index 785c510..ec206ea 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -78,7 +78,7 @@ class _CRGSDRAM(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -120,8 +120,7 @@ class _CRGSDRAM(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # USB PLL diff --git a/litex_boards/targets/lambdaconcept_ecpix5.py b/litex_boards/targets/lambdaconcept_ecpix5.py index 0093925..f6c93ef 100755 --- a/litex_boards/targets/lambdaconcept_ecpix5.py +++ b/litex_boards/targets/lambdaconcept_ecpix5.py @@ -33,7 +33,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -69,8 +69,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset | self.rst), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset | self.rst), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/lattice_ecp5_vip.py b/litex_boards/targets/lattice_ecp5_vip.py index 47cb5d7..f922bb3 100755 --- a/litex_boards/targets/lattice_ecp5_vip.py +++ b/litex_boards/targets/lattice_ecp5_vip.py @@ -32,7 +32,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -67,8 +67,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # HDMI diff --git a/litex_boards/targets/lattice_versa_ecp5.py b/litex_boards/targets/lattice_versa_ecp5.py index c37eb17..d6a1e56 100755 --- a/litex_boards/targets/lattice_versa_ecp5.py +++ b/litex_boards/targets/lattice_versa_ecp5.py @@ -32,7 +32,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -68,8 +68,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # BaseSoC ------------------------------------------------------------------------------------------ diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 653cb82..ea85df6 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -33,7 +33,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -73,8 +73,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # USB PLL diff --git a/litex_boards/targets/rcs_arctic_tern_bmc_card.py b/litex_boards/targets/rcs_arctic_tern_bmc_card.py index 8d18343..c4eb11c 100755 --- a/litex_boards/targets/rcs_arctic_tern_bmc_card.py +++ b/litex_boards/targets/rcs_arctic_tern_bmc_card.py @@ -35,7 +35,7 @@ class _CRG(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_eb = ClockDomain(reset_less=True) self.clock_domains.cd_dvo = ClockDomain(reset_less=True) @@ -83,8 +83,7 @@ class _CRG(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] # Generate DVO clock diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 468e4e7..fafe447 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -60,7 +60,7 @@ class _CRGSDRAM(Module): self.clock_domains.cd_init = ClockDomain() self.clock_domains.cd_por = ClockDomain(reset_less=True) self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) self.clock_domains.cd_sys2x_i = ClockDomain(reset_less=True) # # # @@ -102,8 +102,7 @@ class _CRGSDRAM(Module): i_CLKI = self.cd_sys2x.clk, i_RST = self.reset, o_CDIVX = self.cd_sys.clk), - AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), - AsyncResetSynchronizer(self.cd_sys2x, ~pll.locked | self.reset), + AsyncResetSynchronizer(self.cd_sys, ~pll.locked | self.reset), ] self.comb += platform.request("dram_vtt_en").eq(1)