diff --git a/litex_boards/platforms/gsd_butterstick.py b/litex_boards/platforms/gsd_butterstick.py index c3d6e34..a6d9b33 100644 --- a/litex_boards/platforms/gsd_butterstick.py +++ b/litex_boards/platforms/gsd_butterstick.py @@ -51,7 +51,7 @@ _io_r1_0 = [ Subsignal("data", Pins("C12 A12 D14 A14"), Misc("PULLMODE=UP")), Subsignal("cmd", Pins("A13"), Misc("PULLMODE=UP")), Subsignal("clk", Pins("B13")), - Subsignal("cd", Pins("B15")), + Subsignal("cd", Pins("B15"), Misc("PULLMODE=UP")), Misc("SLEWRATE=FAST"), IOStandard("LVCMOS33"), ), @@ -83,6 +83,11 @@ _io_r1_0 = [ Misc("SLEWRATE=FAST") ), + ("vccio_ctrl", 0, + Subsignal("pdm", Pins("V1 E11 T2")), + Subsignal("en", Pins("E12")) + ), + # RGMII Ethernet ("eth_clocks", 0, Subsignal("tx", Pins("E15")), @@ -102,18 +107,28 @@ _io_r1_0 = [ IOStandard("LVCMOS33"), Misc("SLEWRATE=FAST") ), + + ("ulpi", 0, + Subsignal("data", Pins("B9 C6 A7 E9 A8 D9 C10 C7")), + Subsignal("clk", Pins("B6")), + Subsignal("dir", Pins("A6")), + Subsignal("nxt", Pins("B8")), + Subsignal("stp", Pins("C8")), + Subsignal("rst", Pins("C9")), + IOStandard("LVCMOS18"),Misc("SLEWRATE=FAST") + ), ] # Connectors --------------------------------------------------------------------------------------- _connectors_r1_0 = [ ("SYZYGY0", { - # Single ended IOs. - "S0":"G2", "S1":"J3", - "S2":"F1", "S3":"K3", - "S4":"J4", "S5":"K2", - "S6":"J5", "S7":"J1", - "S8":"N2", "S9":"L3", + # single ended + "S0": "G2", "S1": "J3", + "S2": "F1", "S3": "K3", + "S4": "J4", "S5": "K2", + "S6": "J5", "S7": "J1", + "S8": "N2", "S9": "L3", "S10":"M1", "S11":"L2", "S12":"N3", "S13":"N4", "S14":"M3", "S15":"P5", @@ -125,20 +140,37 @@ _connectors_r1_0 = [ "S26":"P3", "S27":"P4", "S28":"H2", "S29":"P1", "S30":"G1", "S31":"P2", - # Diff pairs IOs. } ), ("SYZYGY1", { - # Single ended IOs. - # Diff pairs IOs. - "D0P":"E4", "D0N":"D5", - "D1P":"A4", "D1N":"A5", - "D2P":"C4", "D2N":"B4", - "D3P":"B2", "D3N":"C2", - "D4P":"A2", "D4N":"B1", - "D5P":"C1", "D5N":"D1", - "D6P":"F4", "D6N":"E3", - "D7P":"D2", "D7N":"E1", + # single ended + "S0": "E4", "S1": "A4", + "S2": "D5", "S3": "A5", + "S4": "C4", "S5": "B2", + "S6": "B4", "S7": "C2", + "S8": "A2", "S9": "C1", + "S10":"B1", "S11":"D1", + "S12":"F4", "S13":"D2", + "S14":"E3", "S15":"E1", + "S16":"B5", "S17":"E5", + "S18":"F5", "S19":"C5", + "S20":"B3", "S21":"A3", + "S22":"D3", "S23":"C3", + "S24":"H5", "S25":"G5", + "S26":"H3", "S27":"H4", + "S28":"G3", "S29":"F2", + "S30":"F3", "S31":"E2", + } + ), + ("SYZYGY2", { + # single ended + "S0": "C11", "S1": "B11", + "S2": "D6", "S3": "D7", + "S4": "E6", "S5": "E7", + "S6": "D8", "S7": "E8", + "S8": "E10", "S9": "D10", + "S10":"A9", "S11":"A10", + "S12":"B10", "S13":"A11" } ), ] diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index fe7202d..c032574 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -28,7 +28,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import MT41K256M16 +from litedram.modules import MT41K64M16,MT41K128M16,MT41K256M16,MT41K512M16 from litedram.phy import ECP5DDRPHY from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII @@ -84,8 +84,9 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, revision="1.0", device="85F", sys_clk_freq=int(60e6), toolchain="trellis", - with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, + def __init__(self, revision="1.0", device="85F", sdram_device="MT41K64M16", sys_clk_freq=int(60e6), + toolchain="trellis", with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", + eth_dynamic_ip=False, with_spi_flash=False, with_led_chaser=True, **kwargs) : @@ -104,6 +105,14 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: + available_sdram_modules = { + "MT41K64M16": MT41K64M16, + "MT41K128M16": MT41K128M16, + "MT41K256M16": MT41K256M16, + "MT41K512M16": MT41K512M16, + } + sdram_module = available_sdram_modules.get(sdram_device) + self.submodules.ddrphy = ECP5DDRPHY( platform.request("ddram"), sys_clk_freq=sys_clk_freq) @@ -111,7 +120,7 @@ class BaseSoC(SoCCore): self.comb += self.crg.reset.eq(self.ddrphy.init.reset) self.add_sdram("sdram", phy = self.ddrphy, - module = MT41K256M16(sys_clk_freq, "1:2"), + module = sdram_module(sys_clk_freq, "1:2"), l2_cache_size = kwargs.get("l2_size", 8192) ) @@ -148,6 +157,7 @@ def main(): parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") parser.add_argument("--revision", default="1.0", help="Board Revision: 1.0 (default)") parser.add_argument("--device", default="85F", help="ECP5 device (default: 85F)") + parser.add_argument("--sdram-device", default="MT41K64M16", help="SDRAM device (default: MT41K64M16)") ethopts = parser.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Add Ethernet") ethopts.add_argument("--with-etherbone", action="store_true", help="Add EtherBone") @@ -168,6 +178,7 @@ def main(): toolchain = args.toolchain, revision = args.revision, device = args.device, + sdram_device = args.sdram_device, sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone,