From 2bff2d42601a65a5ad8a613b7f2940d2b1bd3b97 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Mon, 1 May 2023 09:28:03 -0400 Subject: [PATCH] target/stlv7325-v2: tune eth phy delay --- litex_boards/targets/sitlinv_stlv7325_v2.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/sitlinv_stlv7325_v2.py b/litex_boards/targets/sitlinv_stlv7325_v2.py index 6e5858c..4e72e02 100755 --- a/litex_boards/targets/sitlinv_stlv7325_v2.py +++ b/litex_boards/targets/sitlinv_stlv7325_v2.py @@ -112,8 +112,8 @@ class BaseSoC(SoCCore): self.ethphy = LiteEthPHYRGMII( clock_pads = self.platform.request("eth_clocks", 0), pads = self.platform.request("eth", 0), - tx_delay = 1.48e-9, - rx_delay = 1.48e-9, + tx_delay = 1.417e-9, + rx_delay = 1.417e-9, ) self.add_ethernet(phy=self.ethphy)