From 2c26f07a5a0f47df077d9a5338955077cb732aca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Mon, 17 Jan 2022 16:24:16 +0100 Subject: [PATCH] digilent_cmod_a7: Remove unused clocks. --- litex_boards/targets/digilent_cmod_a7.py | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 918aee2..db4a101 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -35,8 +35,8 @@ class _CRG(Module): self.cpu_reset = Signal() self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) - self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) + #self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + #self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) # # # @@ -49,8 +49,8 @@ class _CRG(Module): pll.register_clkin(plls_clk12, 12e6) pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) - pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) + #pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + #pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst.