From 2c2b3e318a169eee2b4418125090c2d476d18477 Mon Sep 17 00:00:00 2001 From: John Simons Date: Tue, 12 Dec 2023 15:44:51 +0100 Subject: [PATCH] Fixed pinout and first steps adding PCIe support --- litex_boards/platforms/alinx_axau15.py | 6 +++--- litex_boards/targets/alinx_axau15.py | 17 +++++++++++++++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/alinx_axau15.py b/litex_boards/platforms/alinx_axau15.py index d2d4b1a..464c7de 100644 --- a/litex_boards/platforms/alinx_axau15.py +++ b/litex_boards/platforms/alinx_axau15.py @@ -26,8 +26,8 @@ _io = [ ("user_btn_2", 0, Pins("AA23"), IOStandard("LVCMOS33")), # Leds - ("user_led", 0, Pins("W21"), IOStandard("LVCMOS33")), - ("user_led", 1, Pins("AC16"), IOStandard("LVCMOS33")), + ("user_led", 0, Pins("W21"), IOStandard("LVCMOS18")), + ("user_led", 1, Pins("AC16"), IOStandard("LVCMOS18")), # Serial ("serial", 0, @@ -58,7 +58,7 @@ _io = [ Subsignal("we_n", Pins("K26"), IOStandard("SSTL12_DCI")), Subsignal("cs_n", Pins("H23"), IOStandard("SSTL12_DCI")), Subsignal("act_n", Pins("K25"), IOStandard("SSTL12_DCI")), - Subsignal("par", Pins("L24"), IOStandard("SSTL12_DCI")), + #Subsignal("par", Pins("L24"), IOStandard("SSTL12_DCI")), Subsignal("dm", Pins("E25 L18"), IOStandard("POD12_DCI")), Subsignal("dq", Pins( diff --git a/litex_boards/targets/alinx_axau15.py b/litex_boards/targets/alinx_axau15.py index 26c2fab..307f957 100755 --- a/litex_boards/targets/alinx_axau15.py +++ b/litex_boards/targets/alinx_axau15.py @@ -23,6 +23,9 @@ from litex.soc.cores.led import LedChaser from litedram.modules import MT40A512M16 from litedram.phy import usddrphy +from litepcie.phy.usppciephy import USPPCIEPHY +from litepcie.software import generate_litepcie_software + # CRG ---------------------------------------------------------------------------------------------- class _CRG(LiteXModule): @@ -53,6 +56,7 @@ class BaseSoC(SoCCore): with_etherbone = False, eth_ip = "192.168.1.50", with_led_chaser = True, + with_pcie = True, **kwargs): platform = alinx_axau15.Platform() @@ -76,6 +80,14 @@ class BaseSoC(SoCCore): l2_cache_size = kwargs.get("l2_size", 8192) ) + # PCIe ------------------------------------------------------------------------------------- + if with_pcie: + self.pcie_phy = USPPCIEPHY(platform, platform.request("pcie_x4"), + speed = "gen4", + data_width = 256, + bar0_size = 0x20000) + self.add_pcie(phy=self.pcie_phy, ndmas=1) + # TODO: add SFP+ cages for ethernet # Ethernet / Etherbone --------------------------------------------------------------------- # if with_ethernet or with_etherbone: @@ -101,6 +113,8 @@ def main(): from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=alinx_axau15.Platform, description="LiteX SoC on AXAU15.") parser.add_target_argument("--sys-clk-freq", default=125e6, type=float, help="System clock frequency.") + parser.add_argument("--driver", action="store_true", help="Generate LitePCIe driver") + #ethopts = parser.target_group.add_mutually_exclusive_group() #ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") #ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") @@ -125,6 +139,9 @@ def main(): if args.build: builder.build(**parser.toolchain_argdict) + if args.driver: + generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver")) + if args.load: prog = soc.platform.create_programmer() prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))