diff --git a/litex_boards/platforms/gsd_orangecrab.py b/litex_boards/platforms/gsd_orangecrab.py
index 1de8206..0656de3 100644
--- a/litex_boards/platforms/gsd_orangecrab.py
+++ b/litex_boards/platforms/gsd_orangecrab.py
@@ -229,7 +229,7 @@ class Platform(LatticeECP5Platform):
         LatticeECP5Platform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
-        return DFUProg(vid="1209", pid="5af0")
+        return DFUProg(vid="1209", pid="5af0", alt=0)
 
     def do_finalize(self, fragment):
         LatticeECP5Platform.do_finalize(self, fragment)
diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py
index eda48c0..35b6957 100755
--- a/litex_boards/targets/lattice_crosslink_nx_evn.py
+++ b/litex_boards/targets/lattice_crosslink_nx_evn.py
@@ -21,6 +21,7 @@ from litex.build.generic_platform import *
 
 from litex.soc.cores.clock import *
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
@@ -69,6 +70,7 @@ class BaseSoC(SoCCore):
     def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant",
         with_led_chaser = True,
         with_spi_flash  = False,
+        with_uartbone   = False,
         **kwargs):
         platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain)
 
@@ -85,7 +87,7 @@ class BaseSoC(SoCCore):
         # 128KB LRAM (used as SRAM) ---------------------------------------------------------------
         size = 128*kB
         self.spram = NXLRAM(32, size)
-        self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size)
+        self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=size))
 
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
@@ -94,8 +96,7 @@ class BaseSoC(SoCCore):
                 sys_clk_freq = sys_clk_freq)
 
         # UARTBone ---------------------------------------------------------------------------------
-        debug_uart = False
-        if debug_uart:
+        if with_uartbone:
             self.add_uartbone()
 
         # SPI Flash --------------------------------------------------------------------------------
@@ -117,6 +118,7 @@ def main():
     parser.add_target_argument("--address",       default=0x0,                help="Flash address to program bitstream at.")
     parser.add_target_argument("--prog-target",   default="direct",           help="Programming Target (direct or flash).")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
+    parser.add_target_argument("--with-uartbone", action="store_true",        help="Add UartBone on 1st serial.")
     args = parser.parse_args()
 
     soc = BaseSoC(
@@ -124,6 +126,7 @@ def main():
         device       = args.device,
         toolchain    = args.toolchain,
         with_spi_flash = args.with_spi_flash,
+        with_uartbone = args.with_uartbone,
         **parser.soc_argdict
     )
     builder = Builder(soc, **parser.builder_argdict)