From 3c0b6956cca9d70b2c0367224b11eee22045a79c Mon Sep 17 00:00:00 2001 From: Josuah Demangeon Date: Wed, 9 Aug 2023 18:05:22 +0200 Subject: [PATCH 1/2] platforms/crosslink_nx_evn: Fix 5412d0e always disabling uartbone Also fix a warning about register_mem being deprecated, taking inspiration from platforms/crosslink_nx_vip --- litex_boards/targets/lattice_crosslink_nx_evn.py | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index 4775f1b..0e91f77 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -21,6 +21,7 @@ from litex.build.generic_platform import * from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * +from litex.soc.integration.soc import SoCRegion from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser @@ -68,6 +69,7 @@ class BaseSoC(SoCCore): } def __init__(self, sys_clk_freq=75e6, device="LIFCL-40-9BG400C", toolchain="radiant", with_led_chaser = True, + with_uartbone = False, **kwargs): platform = lattice_crosslink_nx_evn.Platform(device=device, toolchain=toolchain) @@ -84,7 +86,7 @@ class BaseSoC(SoCCore): # 128KB LRAM (used as SRAM) --------------------------------------------------------------- size = 128*kB self.spram = NXLRAM(32, size) - self.register_mem("sram", self.mem_map["sram"], self.spram.bus, size) + self.bus.add_slave("sram", self.spram.bus, SoCRegion(origin=self.mem_map["sram"], size=size)) # Leds ------------------------------------------------------------------------------------- if with_led_chaser: @@ -93,8 +95,7 @@ class BaseSoC(SoCCore): sys_clk_freq = sys_clk_freq) # UARTBone --------------------------------------------------------------------------------- - debug_uart = False - if debug_uart: + if with_uartbone: self.add_uartbone() @@ -109,12 +110,14 @@ def main(): parser.add_target_argument("--programmer", default="radiant", help="Programmer (radiant or ecpprog).") parser.add_target_argument("--address", default=0x0, help="Flash address to program bitstream at.") parser.add_target_argument("--prog-target", default="direct", help="Programming Target (direct or flash).") + parser.add_target_argument("--with-uartbone", action="store_true", help="Add UartBone on 1st serial.") args = parser.parse_args() soc = BaseSoC( sys_clk_freq = args.sys_clk_freq, device = args.device, toolchain = args.toolchain, + with_uartbone = args.with_uartbone, **parser.soc_argdict ) builder = Builder(soc, **parser.builder_argdict) From 5799c352470daeb96541285af6cea0aa6827ef9a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 28 Aug 2023 16:27:46 +0200 Subject: [PATCH 2/2] platforms/gsd_orangecrab: Set alt point to DFUProg. --- litex_boards/platforms/gsd_orangecrab.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/gsd_orangecrab.py b/litex_boards/platforms/gsd_orangecrab.py index 1de8206..0656de3 100644 --- a/litex_boards/platforms/gsd_orangecrab.py +++ b/litex_boards/platforms/gsd_orangecrab.py @@ -229,7 +229,7 @@ class Platform(LatticeECP5Platform): LatticeECP5Platform.__init__(self, f"LFE5U-{device}-8MG285C", io, connectors, toolchain=toolchain, **kwargs) def create_programmer(self): - return DFUProg(vid="1209", pid="5af0") + return DFUProg(vid="1209", pid="5af0", alt=0) def do_finalize(self, fragment): LatticeECP5Platform.do_finalize(self, fragment)