diff --git a/litex_boards/platforms/sipeed_tang_primer.py b/litex_boards/platforms/sipeed_tang_primer.py
new file mode 100644
index 0000000..2b0f6aa
--- /dev/null
+++ b/litex_boards/platforms/sipeed_tang_primer.py
@@ -0,0 +1,53 @@
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
+# SPDX-License-Identifier: BSD-2-Clause
+
+from migen import *
+
+from litex.build.generic_platform import *
+from litex.build.anlogic.platform import AnlogicPlatform
+from litex.build.openfpgaloader import OpenFPGALoader
+
+# IOs ----------------------------------------------------------------------------------------------
+
+_io = [
+    # Clk / Rst
+    ("clk24",  0, Pins("K14"), IOStandard("LVCMOS33")),
+
+    # RGB LED
+    ("user_led", 0, Pins("R3"), IOStandard("LVCMOS33")),  # R
+    ("user_led", 1, Pins("J14"), IOStandard("LVCMOS33")), # G
+    ("user_led", 2, Pins("P13"), IOStandard("LVCMOS33")), # B
+
+    # Buttons.
+    ("user_btn", 0, Pins("K16"),  IOStandard("LVCMOS33")), # USER_KEY
+
+    # Serial
+    ("serial", 0,
+        Subsignal("tx", Pins("J13")),
+        Subsignal("rx", Pins("H13")),
+        IOStandard("LVCMOS33")
+    ),
+]
+
+# Connectors ---------------------------------------------------------------------------------------
+
+_connectors = []
+
+# Platform -----------------------------------------------------------------------------------------
+
+class Platform(AnlogicPlatform):
+    default_clk_name   = "clk24"
+    default_clk_period = 1e9/24e6
+
+    def __init__(self):
+        AnlogicPlatform.__init__(self, "EG4S20BG256", _io, _connectors, toolchain="td")
+
+    def create_programmer(self):
+        return OpenFPGALoader("licheeTang")
+
+    def do_finalize(self, fragment):
+        AnlogicPlatform.do_finalize(self, fragment)
+        self.add_period_constraint(self.lookup_request("clk24", loose=True), 1e9/24e6)
diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py
new file mode 100755
index 0000000..df0a981
--- /dev/null
+++ b/litex_boards/targets/sipeed_tang_primer.py
@@ -0,0 +1,93 @@
+#!/usr/bin/env python3
+
+#
+# This file is part of LiteX-Boards.
+#
+# Copyright (c) 2021 Miodrag Milanovic <mmicko@gmail.com>
+# SPDX-License-Identifier: BSD-2-Clause
+
+
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from litex_boards.platforms import sipeed_tang_primer
+
+from litex.build.generic_platform import *
+
+from litex.soc.cores.clock import *
+from litex.soc.integration.soc_core import *
+from litex.soc.integration.builder import *
+from litex.soc.cores.led import LedChaser
+
+
+# CRG ----------------------------------------------------------------------------------------------
+
+class _CRG(Module):
+    def __init__(self, platform, sys_clk_freq):
+        self.clock_domains.cd_sys   = ClockDomain()
+
+        # # #
+
+        # Clk / Rst.
+        clk24 = platform.request("clk24")
+        rst_n = platform.request("user_btn", 0)
+
+        self.comb += self.cd_sys.clk.eq(clk24)
+        self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
+
+# BaseSoC ------------------------------------------------------------------------------------------
+
+class BaseSoC(SoCCore):
+    def __init__(self, sys_clk_freq=int(24e6), with_led_chaser=True, **kwargs):
+        platform = sipeed_tang_primer.Platform()
+
+        # SoCCore ----------------------------------------------------------------------------------
+        SoCCore.__init__(self, platform, sys_clk_freq,
+            ident         = "LiteX SoC on Tang Primer",
+            ident_version = True,
+            **kwargs
+        )
+
+        # CRG --------------------------------------------------------------------------------------
+        self.submodules.crg = _CRG(platform, sys_clk_freq)
+
+        # Leds -------------------------------------------------------------------------------------
+        if with_led_chaser:
+            self.submodules.leds = LedChaser(
+                pads         = platform.request_all("user_led"),
+                sys_clk_freq = sys_clk_freq)
+
+# Build --------------------------------------------------------------------------------------------
+
+def main():
+    parser = argparse.ArgumentParser(description="LiteX SoC on Tang Primer")
+    parser.add_argument("--build",       action="store_true", help="Build bitstream")
+    parser.add_argument("--load",        action="store_true", help="Load bitstream")
+    parser.add_argument("--flash",       action="store_true", help="Flash Bitstream")
+    parser.add_argument("--sys-clk-freq",default=24e6,        help="System clock frequency (default: 24MHz)")
+    builder_args(parser)
+    soc_core_args(parser)
+    args = parser.parse_args()
+
+    soc = BaseSoC(
+        sys_clk_freq      = int(float(args.sys_clk_freq)),
+        **soc_core_argdict(args)
+    )
+
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build(run=args.build)
+
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+
+    if args.flash:
+        prog = soc.platform.create_programmer()
+        prog.flash(0, os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
+        
+
+
+if __name__ == "__main__":
+    main()