From 2ce24df76dda20cff9ac40c334300d5dc1311d60 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 18 Jul 2020 22:18:41 +0200 Subject: [PATCH] platforms/genesys2: add internal_vref to 0.750v on bank 34 (DDR3). --- litex_boards/platforms/genesys2.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/platforms/genesys2.py b/litex_boards/platforms/genesys2.py index 8ddabaa..072b951 100644 --- a/litex_boards/platforms/genesys2.py +++ b/litex_boards/platforms/genesys2.py @@ -145,6 +145,7 @@ class Platform(XilinxPlatform): def __init__(self): XilinxPlatform.__init__(self, "xc7k325t-ffg900-2", _io, _connectors, toolchain="vivado") + self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") def create_programmer(self): return OpenOCD("openocd_genesys2.cfg", "bscan_spi_xc7a325t.bit")