From 2cef54a9093fcc499ec6e83cbdba4291b67d40c4 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 26 Jul 2020 11:58:42 +0200 Subject: [PATCH] targets/colorlight_5a_75x: avoid sys_clk_freq of 125MHz with etherbone (no longer required). This allows creating SoCs with CPU, SDRAM and Etherbone enabled all together. --- litex_boards/targets/colorlight_5a_75x.py | 3 --- 1 file changed, 3 deletions(-) diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 26019da..9a818ff 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -103,9 +103,6 @@ class BaseSoC(SoCCore): elif board == "5a-75e": platform = colorlight_5a_75e.Platform(revision=revision) - if with_etherbone: - sys_clk_freq = int(125e6) - # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Colorlight " + board.upper(),