From 2d3422869c14af8c4df9deb2bba2112df8372e9a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 14 Nov 2021 09:19:19 +0100 Subject: [PATCH] quicklogic_quickfeather: Update clocking. --- litex_boards/targets/quicklogic_quickfeather.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index e5101e3..f452590 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -32,8 +32,8 @@ class _CRG(Module): class Open(Signal): pass if is_eoss3_cpu: - self.comb += ClockSignal("sys").eq(ClockSignal("Sys_Clk0")) - self.comb += ResetSignal("sys").eq(ResetSignal("Sys_Clk0") | self.rst) + self.comb += ClockSignal("sys").eq(ClockSignal("eos_s3_0")) + self.comb += ResetSignal("sys").eq(ResetSignal("eos_s3_0") | self.rst) else: self.specials += Instance("qlal4s3b_cell_macro", o_Sys_Clk0 = self.cd_sys.clk,