From 2d3b81a532d02d316b529139727957d5c93af737 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 27 Jul 2023 11:52:40 +0200 Subject: [PATCH] efinix_trion_t120_bga576: Add Ethernet through RGMII PMOD and switch to it. See https://github.com/enjoy-digital/liteeth/issues/66#issuecomment-859366899 for the PMOD. --- .../efinix_trion_t120_bga576_dev_kit.py | 70 +++++++++++++------ 1 file changed, 50 insertions(+), 20 deletions(-) diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index f06dfd4..5417101 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -27,7 +27,7 @@ from liteeth.phy.trionrgmii import LiteEthPHYRGMII class _CRG(LiteXModule): def __init__(self, platform, sys_clk_freq): - self.rst = Signal() + #self.rst = Signal() self.cd_sys = ClockDomain() # # # @@ -38,7 +38,8 @@ class _CRG(LiteXModule): # PLL self.pll = pll = TRIONPLL(platform) - self.comb += pll.reset.eq(~rst_n | self.rst) + #self.comb += pll.reset.eq(~rst_n | self.rst) + self.comb += pll.reset.eq(~rst_n) pll.register_clkin(clk40, 40e6) pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=True, name="axi_clk") @@ -50,6 +51,7 @@ class BaseSoC(SoCCore): with_ethernet = False, with_etherbone = False, eth_phy = 0, + eth_rmii_pmod = True, eth_ip = "192.168.1.50", with_led_chaser = True, **kwargs): @@ -90,23 +92,51 @@ class BaseSoC(SoCCore): # Ethernet / Etherbone --------------------------------------------------------------------- if with_ethernet or with_etherbone: - self.ethphy = LiteEthPHYRGMII( - platform = platform, - clock_pads = platform.request("eth_clocks", eth_phy), - pads = platform.request("eth", eth_phy), - with_hw_init_reset = False) + # Use board's Ethernet PHYs. + if not eth_rmii_pmod: + self.ethphy = LiteEthPHYRGMII( + platform = platform, + clock_pads = platform.request("eth_clocks", eth_phy), + pads = platform.request("eth", eth_phy), + with_hw_init_reset = False) + # FIXME: Avoid this. + platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").tx) + platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").rx) + platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_data) + platform.toolchain.excluded_ios.append(platform.lookup_request("eth").rx_data) + platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio) + # Use Ethernet RMII PMOD. + else: + from litex.build.generic_platform import Pins, Subsignal, IOStandard + def eth_lan8720_rmii_pmod_io(pmod): + # Lan8020 RMII PHY "PMOD": To be used as a PMOD, MDIO should be disconnected and TX1 connected to PMOD8 IO. + return [ + ("eth_rmii_clocks", 0, + Subsignal("ref_clk", Pins(f"{pmod}:6")), + IOStandard("3.3_V_LVTTL_/_LVCMOS"), + ), + ("eth_rmii", 0, + Subsignal("rx_data", Pins(f"{pmod}:5 {pmod}:1")), + Subsignal("crs_dv", Pins(f"{pmod}:2")), + Subsignal("tx_en", Pins(f"{pmod}:4")), + Subsignal("tx_data", Pins(f"{pmod}:0 {pmod}:7")), + IOStandard("3.3_V_LVTTL_/_LVCMOS") + ), + ] + platform.add_extension(eth_lan8720_rmii_pmod_io("pmod_d")) + + from liteeth.phy.rmii import LiteEthPHYRMII + self.ethphy = LiteEthPHYRMII( + clock_pads = platform.request("eth_rmii_clocks"), + pads = platform.request("eth_rmii"), + refclk_cd = None + ) + if with_ethernet: self.add_ethernet(phy=self.ethphy, software_debug=False) if with_etherbone: self.add_etherbone(phy=self.ethphy) - # FIXME: Avoid this. - platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").tx) - platform.toolchain.excluded_ios.append(platform.lookup_request("eth_clocks").rx) - platform.toolchain.excluded_ios.append(platform.lookup_request("eth").tx_data) - platform.toolchain.excluded_ios.append(platform.lookup_request("eth").rx_data) - platform.toolchain.excluded_ios.append(platform.lookup_request("eth").mdio) - # LPDDR3 SDRAM ----------------------------------------------------------------------------- if not self.integrated_main_ram_size: # DRAM / PLL Blocks. @@ -328,12 +358,12 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"}) self.submodules += axi.AXILite2AXI(axi_lite_port, axi_port) self.bus.add_slave(f"target{n}", axi_lite_port, SoCRegion(origin=0x4000_0000 + 0x1000_0000*n, size=0x1000_0000)) # 256MB. - # Use DRAM's target0 port as Main Ram ----------------------------------------------------- - self.bus.add_region("main_ram", SoCRegion( - origin = 0x4000_0000, - size = 0x1000_0000, # 256MB. - linker = True) - ) + # Use DRAM's target0 port as Main Ram ----------------------------------------------------- + self.bus.add_region("main_ram", SoCRegion( + origin = 0x4000_0000, + size = 0x1000_0000, # 256MB. + linker = True) + ) # Build --------------------------------------------------------------------------------------------