From 2d9543b65ea67e0759ea1ee9ab34630917a819e3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Tue, 5 May 2020 15:11:38 +0200 Subject: [PATCH] targets: add build/load parameters on all targets. --- litex_boards/targets/ac701.py | 18 +++++----- litex_boards/targets/aller.py | 9 ++++- litex_boards/targets/arty.py | 14 +++++--- litex_boards/targets/arty_s7.py | 10 ++++-- litex_boards/targets/c10lprefkit.py | 11 ++++-- litex_boards/targets/camlink_4k.py | 11 ++++-- litex_boards/targets/colorlight_5a_75b.py | 42 +++++++---------------- litex_boards/targets/de0nano.py | 8 ++++- litex_boards/targets/de10lite.py | 10 ++++-- litex_boards/targets/de10nano.py | 12 ++++--- litex_boards/targets/de1soc.py | 8 ++++- litex_boards/targets/de2_115.py | 8 ++++- litex_boards/targets/ecp5_evn.py | 21 +++++++----- litex_boards/targets/ecpix5.py | 34 +++++------------- litex_boards/targets/fomu.py | 20 ++++------- litex_boards/targets/genesys2.py | 8 ++++- litex_boards/targets/hadbadge.py | 14 ++++---- litex_boards/targets/icebreaker.py | 19 ++++++---- litex_boards/targets/kc705.py | 11 ++++-- litex_boards/targets/kcu105.py | 11 ++++-- litex_boards/targets/kx2.py | 8 ++++- litex_boards/targets/linsn_rv901t.py | 12 +++++-- litex_boards/targets/mercury_xu5.py | 8 ++++- litex_boards/targets/mimas_a7.py | 10 ++++-- litex_boards/targets/minispartan6.py | 8 ++++- litex_boards/targets/nereid.py | 11 ++++-- litex_boards/targets/netv2.py | 11 ++++-- litex_boards/targets/nexys4ddr.py | 14 +++++--- litex_boards/targets/nexys_video.py | 11 ++++-- litex_boards/targets/orangecrab.py | 19 +++++----- litex_boards/targets/pipistrello.py | 8 ++++- litex_boards/targets/simple.py | 13 ++++--- litex_boards/targets/tagus.py | 9 ++++- litex_boards/targets/trellisboard.py | 21 +++++++----- litex_boards/targets/ulx3s.py | 21 +++++++----- litex_boards/targets/vc707.py | 8 ++++- litex_boards/targets/vcu118.py | 8 ++++- litex_boards/targets/versa_ecp5.py | 18 ++++++---- litex_boards/targets/zcu104.py | 8 ++++- 39 files changed, 329 insertions(+), 196 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 0d5808f..26ce9a3 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -115,18 +116,19 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on AC701") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("--ethernet-phy", default="rgmii", - help="select Ethernet PHY (rgmii or 1000basex)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--ethernet-phy", default="rgmii", help="Select Ethernet PHY (rgmii or 1000basex)") args = parser.parse_args() - soc = BaseSoC(with_ethernet=args.with_ethernet, - ethernet_phy=args.ethernet_phy, - **soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, ethernet_phy=args.ethernet_phy, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/aller.py b/litex_boards/targets/aller.py index 7f4b746..204841a 100755 --- a/litex_boards/targets/aller.py +++ b/litex_boards/targets/aller.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse import sys @@ -169,6 +170,8 @@ class PCIeSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Aller") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -180,8 +183,12 @@ def main(): platform = aller.Platform() soc = PCIeSoC(platform, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - vns = builder.build() + vns = builder.build(run=args.build) soc.generate_software_headers() + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + if __name__ == "__main__": main() diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index aa20f60..0613115 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -96,20 +97,25 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Arty") + parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") args = parser.parse_args() assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**vivado_build_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/arty_s7.py b/litex_boards/targets/arty_s7.py index b816d1d..acb9f8c 100755 --- a/litex_boards/targets/arty_s7.py +++ b/litex_boards/targets/arty_s7.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2020 Staf Verhaegen # License: BSD +import os import argparse from migen import * @@ -75,7 +76,9 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Arty") + parser = argparse.ArgumentParser(description="LiteX SoC on Arty S7") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) @@ -83,8 +86,11 @@ def main(): soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**vivado_build_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index 009e863..9b3c10a 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -92,16 +93,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on C10 LP RefKit") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index af50330..7fd2977 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -99,8 +99,9 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Cam Link 4K") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -109,7 +110,11 @@ def main(): soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/colorlight_5a_75b.py b/litex_boards/targets/colorlight_5a_75b.py index d8f7215..da321d2 100755 --- a/litex_boards/targets/colorlight_5a_75b.py +++ b/litex_boards/targets/colorlight_5a_75b.py @@ -34,6 +34,7 @@ # Etherbone stack that need to be optimized. It was initially just used to validate the reversed # pinout but happens to work on hardware... +import os import argparse import sys @@ -133,25 +134,6 @@ class BaseSoC(SoCCore): self.add_csr("ethphy") self.add_etherbone(phy=self.ethphy) -# Load --------------------------------------------------------------------------------------------- - -def load(): - import os - f = open("openocd.cfg", "w") - f.write( -""" -interface ftdi -ftdi_vid_pid 0x0403 0x6011 -ftdi_channel 0 -ftdi_layout_init 0x0098 0x008b -reset_config none -adapter_khz 25000 -jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043 -""") - f.close() - os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_colorlight_5a_75b/gateware/top.svf; exit\"") - exit() - # Build -------------------------------------------------------------------------------------------- def main(): @@ -159,17 +141,15 @@ def main(): builder_args(parser) soc_core_args(parser) trellis_args(parser) - parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1") - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support") - parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") - parser.add_argument("--load", action="store_true", help="load bitstream") - parser.add_argument("--sys-clk-freq", default=60e6, help="system clock frequency (default=60MHz)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--revision", default="7.0", type=str, help="Board revision 7.0 (default) or 6.1") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") + parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)") args = parser.parse_args() - if args.load: - load() - assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC(revision=args.revision, with_ethernet = args.with_ethernet, @@ -177,7 +157,11 @@ def main(): sys_clk_freq = args.sys_clk_freq, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**trellis_argdict(args)) + builder.build(**trellis_argdict(args), run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/de0nano.py b/litex_boards/targets/de0nano.py index 3a48cfd..d17a1b3 100755 --- a/litex_boards/targets/de0nano.py +++ b/litex_boards/targets/de0nano.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2020 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -70,14 +71,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE0 Nano") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/de10lite.py b/litex_boards/targets/de10lite.py index ce3917e..6bd31c4 100755 --- a/litex_boards/targets/de10lite.py +++ b/litex_boards/targets/de10lite.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 msloniewski # License: BSD +import os import argparse from migen import * @@ -100,16 +101,21 @@ class VGASoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Lite") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-vga", action="store_true", help="enable VGA support") + parser.add_argument("--with-vga", action="store_true", help="Enable VGA support") args = parser.parse_args() cls = VGASoC if args.with_vga else BaseSoC soc = cls(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/de10nano.py b/litex_boards/targets/de10nano.py index 7c63adc..d315a42 100755 --- a/litex_boards/targets/de10nano.py +++ b/litex_boards/targets/de10nano.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2020 Paul Sajna # License: BSD +import os import argparse from migen import * @@ -83,19 +84,22 @@ class MiSTerSDRAMSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE10 Nano") - parser.add_argument("--with-mister-sdram", action="store_true", - help="enable MiSTer SDRAM expansion board") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) + parser.add_argument("--with-mister-sdram", action="store_true", help="Enable MiSTer SDRAM expansion board") args = parser.parse_args() - soc = None if args.with_mister_sdram: soc = MiSTerSDRAMSoC(**soc_sdram_argdict(args)) else: soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/de1soc.py b/litex_boards/targets/de1soc.py index eb445c5..a0d3c12 100755 --- a/litex_boards/targets/de1soc.py +++ b/litex_boards/targets/de1soc.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 Antony Pavlov # License: BSD +import os import argparse from migen import * @@ -70,14 +71,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE1-SoC") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/de2_115.py b/litex_boards/targets/de2_115.py index 290c392..5e861fa 100755 --- a/litex_boards/targets/de2_115.py +++ b/litex_boards/targets/de2_115.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -70,14 +71,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on DE2-115") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.sof")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/ecp5_evn.py b/litex_boards/targets/ecp5_evn.py index 0615cb0..80c4fde 100755 --- a/litex_boards/targets/ecp5_evn.py +++ b/litex_boards/targets/ecp5_evn.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 Arnaud Durand # License: BSD +import os import argparse from migen import * @@ -54,23 +55,25 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECP5 Evaluation Board") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_core_args(parser) - parser.add_argument("--sys-clk-freq", default=60e6, - help="system clock frequency (default=60MHz)") - parser.add_argument("--x5-clk-freq", type=int, - help="use X5 oscillator as system clock at the specified frequency") + parser.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default=60MHz)") + parser.add_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency") args = parser.parse_args() - cls = BaseSoC - soc = cls(toolchain=args.toolchain, + soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), x5_clk_freq = args.x5_clk_freq, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/ecpix5.py b/litex_boards/targets/ecpix5.py index 2a0d250..8ad8c1b 100755 --- a/litex_boards/targets/ecpix5.py +++ b/litex_boards/targets/ecpix5.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD +import os import argparse import sys @@ -110,42 +111,25 @@ class BaseSoC(SoCCore): for c in "rgb": self.comb += getattr(rgb_led_pads, c).eq(1) -# Load --------------------------------------------------------------------------------------------- - -def load(): - import os - f = open("openocd.cfg", "w") - f.write( -""" -interface ftdi -ftdi_vid_pid 0x0403 0x6010 -ftdi_channel 0 -ftdi_layout_init 0x00e8 0x60eb -reset_config none -adapter_khz 25000 -jtag newtap ecp5 tap -irlen 8 -expected-id 0x41111043 -""") - f.close() - os.system("openocd -f openocd.cfg -c \"transport select jtag; init; svf soc_basesoc_ecpix5/gateware/top.svf; exit\"") - exit() - # Build -------------------------------------------------------------------------------------------- def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ECPIX-5") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_core_args(parser) trellis_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--load", action="store_true", help="load bitstream") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() - if args.load: - load() - soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**trellis_argdict(args)) + builder.build(**trellis_argdict(args), run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/fomu.py b/litex_boards/targets/fomu.py index 5df1fb0..9486cf8 100755 --- a/litex_boards/targets/fomu.py +++ b/litex_boards/targets/fomu.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2018 David Shah # License: BSD +import os import argparse from migen import * @@ -279,24 +280,17 @@ def add_dfu_suffix(fn): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Fomu") - parser.add_argument( - "--board", choices=["evt", "pvt", "hacker"], required=True, - help="build for a particular hardware board" - ) - parser.add_argument( - "--seed", default=0, help="seed to use in nextpnr" - ) - parser.add_argument( - "--placer", default="heap", choices=["sa", "heap"], help="which placer to use in nextpnr" - ) + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--board", choices=["evt", "pvt", "hacker"], required=True, help="Build for a particular hardware board") + parser.add_argument("--seed", default=0, help="Seed to use in Nextpnr") + parser.add_argument("--placer", default="heap", choices=["sa", "heap"], help="Which placer to use in Nextpnr") builder_args(parser) soc_core_args(parser) args = parser.parse_args() - soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed, - debug=True, **soc_core_argdict(args)) + soc = BaseSoC(board=args.board, pnr_placer=args.placer, pnr_seed=args.seed, debug=True, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) if __name__ == "__main__": main() diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 0aa3330..8a80ba4 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -87,6 +88,8 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") @@ -97,8 +100,11 @@ def main(): soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/hadbadge.py b/litex_boards/targets/hadbadge.py index 6eda0de..5a81eef 100755 --- a/litex_boards/targets/hadbadge.py +++ b/litex_boards/targets/hadbadge.py @@ -6,6 +6,7 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD +import os import argparse import sys @@ -78,21 +79,18 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Hackaday Badge") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") - parser.add_argument("--sys-clk-freq", default=48e6, - help="system clock frequency (default=48MHz)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) args = parser.parse_args() - soc = BaseSoC(toolchain=args.toolchain, - sys_clk_freq=int(float(args.sys_clk_freq)), - **soc_sdram_argdict(args)) + soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) if __name__ == "__main__": main() diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index 7c55831..557c7ab 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -14,6 +14,7 @@ # with more features, examples to run C/Rust code on the RISC-V CPU and documentation can be found # at: https://github.com/icebreaker-fpga/icebreaker-litex-examples +import os import argparse from migen import * @@ -115,18 +116,24 @@ def flash(bios_flash_offset): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker") - parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash") - parser.add_argument("--flash", action="store_true", help="Load Bitstream") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash") + parser.add_argument("--flash", action="store_true", help="Flash Bitstream") builder_args(parser) soc_core_args(parser) args = parser.parse_args() + soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bin")) + if args.flash: flash(args.bios_flash_offset) - soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args)) - builder = Builder(soc, **builder_argdict(args)) - builder.build() - if __name__ == "__main__": main() diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index b500c79..5434faf 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2014-2015 Yann Sionneau # License: BSD +import os import argparse from migen import * @@ -83,16 +84,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KC705") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index 2df10a5..fef1b4e 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -92,16 +93,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KCU105") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/kx2.py b/litex_boards/targets/kx2.py index fabd2bc..66c1068 100755 --- a/litex_boards/targets/kx2.py +++ b/litex_boards/targets/kx2.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2020 Mark Standke # License: BSD +import os import argparse from migen import * @@ -71,14 +72,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on KX2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index f948fee..76fb4dd 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019-2020 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -104,10 +105,12 @@ class EthernetSoC(BaseSoC): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Linsn RV901T") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") - parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)") args = parser.parse_args() if args.with_ethernet: @@ -115,8 +118,11 @@ def main(): else: soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 875dcd9..ff5f694 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2020 Antmicro # License: BSD +import os import argparse from migen import * @@ -81,14 +82,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Enclustra's Mercury XU5") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 3d911df..8441f14 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2020 Feliks Montez # License: BSD +import os import argparse from migen import * @@ -83,16 +84,21 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Mimas A7") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) - parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build(**vivado_build_argdict(args)) + builder.build(**vivado_build_argdict(args), run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/minispartan6.py b/litex_boards/targets/minispartan6.py index 7435493..500d822 100755 --- a/litex_boards/targets/minispartan6.py +++ b/litex_boards/targets/minispartan6.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2014 Yann Sionneau # License: BSD +import os import argparse from fractions import Fraction @@ -69,14 +70,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/nereid.py b/litex_boards/targets/nereid.py index 35038f2..b9db14b 100755 --- a/litex_boards/targets/nereid.py +++ b/litex_boards/targets/nereid.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse import sys @@ -166,7 +167,9 @@ class PCIeSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") + parser = argparse.ArgumentParser(description="LiteX SoC on Nereid") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -178,8 +181,12 @@ def main(): platform = nereid.Platform() soc = PCIeSoC(platform, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - vns = builder.build() + vns = builder.build(run=args.build) soc.generate_software_headers() + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + if __name__ == "__main__": main() diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 817fac0..90393ee 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -84,16 +85,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 6137f32..881dfa9 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2018-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -83,20 +84,23 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, - help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index c62d6a1..ce01f16 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2015-2019 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -83,16 +84,20 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index f5b3e62..715707f 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -3,6 +3,7 @@ # This file is Copyright (c) Greg Davill # License: BSD +import os import argparse from migen import * @@ -130,25 +131,21 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on OrangeCrab") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=48e6, - help="system clock frequency (default=48MHz)") - parser.add_argument("--revision", default="0.2", - help="Board Revision {0.1, 0.2} (default=0.2)") - parser.add_argument("--device", default="25F", - help="ECP5 device (default=25F)") - parser.add_argument("--sdram-device", default="MT41K64M16", - help="ECP5 device (default=MT41K64M16)") + parser.add_argument("--sys-clk-freq", default=48e6, help="System clock frequency (default=48MHz)") + parser.add_argument("--revision", default="0.2", help="Board Revision {0.1, 0.2} (default=0.2)") + parser.add_argument("--device", default="25F", help="ECP5 device (default=25F)") + parser.add_argument("--sdram-device", default="MT41K64M16", help="ECP5 device (default=MT41K64M16)") args = parser.parse_args() soc = BaseSoC(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) if __name__ == "__main__": main() diff --git a/litex_boards/targets/pipistrello.py b/litex_boards/targets/pipistrello.py index 9298ac9..9a989ba 100755 --- a/litex_boards/targets/pipistrello.py +++ b/litex_boards/targets/pipistrello.py @@ -7,6 +7,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse from fractions import Fraction @@ -185,14 +186,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Pipistrello") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index b208544..70872bb 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq # License: BSD +import os import argparse import importlib @@ -41,14 +42,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="Generic LiteX SoC") + parser.add_argument("--build", action="store_true", help="Build bitstream") builder_args(parser) soc_core_args(parser) - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("platform", - help="module name of the platform to build for") - parser.add_argument("--gateware-toolchain", default=None, - help="FPGA gateware toolchain used for build") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("platform", help="Module name of the platform to build for") + parser.add_argument("--gateware-toolchain", default=None, help="FPGA gateware toolchain used for build") args = parser.parse_args() platform_module = importlib.import_module(args.platform) @@ -58,7 +57,7 @@ def main(): platform = platform_module.Platform() soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) if __name__ == "__main__": diff --git a/litex_boards/targets/tagus.py b/litex_boards/targets/tagus.py index 15dc4ff..d5ec4e7 100755 --- a/litex_boards/targets/tagus.py +++ b/litex_boards/targets/tagus.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 Florent Kermarrec # License: BSD +import os import argparse import sys @@ -167,6 +168,8 @@ class PCIeSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Tagus") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() @@ -178,8 +181,12 @@ def main(): platform = tagus.Platform() soc = PCIeSoC(platform, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - vns = builder.build() + vns = builder.build(run=args.build) soc.generate_software_headers() + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) + if __name__ == "__main__": main() diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 73db1a9..70a1cdd 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -3,6 +3,7 @@ # This file is Copyright (c) 2019 David Shah # License: BSD +import os import argparse from migen import * @@ -115,17 +116,15 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Trellis Board") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, - help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") - parser.add_argument("--with-spi-sdcard", action="store_true", - help="enable SPI-mode SDCard support") + parser.add_argument("--sys-clk-freq", default=75e6, help="system clock frequency (default=75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="enable SPI-mode SDCard support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), @@ -135,7 +134,11 @@ def main(): soc.add_spi_sdcard() builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/ulx3s.py b/litex_boards/targets/ulx3s.py index e0bbf4c..cfa6e09 100755 --- a/litex_boards/targets/ulx3s.py +++ b/litex_boards/targets/ulx3s.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2018 David Shah # License: BSD +import os import argparse import sys @@ -92,14 +93,12 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") - parser.add_argument("--device", dest="device", default="LFE5U-45F", - help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") - parser.add_argument("--sys-clk-freq", default=50e6, - help="system clock frequency (default=50MHz)") - parser.add_argument("--sdram-module", default="MT48LC16M16", - help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--device", dest="device", default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F") + parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency (default=50MHz)") + parser.add_argument("--sdram-module", default="MT48LC16M16", help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) @@ -111,7 +110,11 @@ def main(): **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/vc707.py b/litex_boards/targets/vc707.py index 6ad60d7..0f7f4db 100755 --- a/litex_boards/targets/vc707.py +++ b/litex_boards/targets/vc707.py @@ -5,6 +5,7 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -71,14 +72,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on VC707") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 8dc09be..b71fd32 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2020 Florent Kermarrec # License: BSD +import os import argparse from migen import * @@ -81,14 +82,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on VCU118") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 6618093..13e13ee 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2018-2019 David Shah # License: BSD +import os import argparse from migen import * @@ -109,21 +110,24 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5") - parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", - help="gateware toolchain to use, trellis (default) or diamond") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--gateware-toolchain", dest="toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond") builder_args(parser) soc_sdram_args(parser) trellis_args(parser) - parser.add_argument("--sys-clk-freq", default=75e6, - help="system clock frequency (default=75MHz)") - parser.add_argument("--with-ethernet", action="store_true", - help="enable Ethernet support") + parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default=75MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} - builder.build(**builder_kargs) + builder.build(**builder_kargs, run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.svf")) if __name__ == "__main__": main() diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 862942a..3bcb037 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -4,6 +4,7 @@ # This file is Copyright (c) 2019 David Shah # License: BSD +import os import argparse from migen import * @@ -80,14 +81,19 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on ZCU104") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") builder_args(parser) soc_sdram_args(parser) args = parser.parse_args() soc = BaseSoC(**soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) - builder.build() + builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, "top.bit")) if __name__ == "__main__": main()