From 2dff854b7a1d794e5d49019dd71fc99926cea05e Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 2 Jul 2021 15:52:12 +0200 Subject: [PATCH] decklink_quad_hdmi_recorder: Enable second DDR3 module. --- litex_boards/targets/decklink_quad_hdmi_recorder.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index 946df46..04730e4 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -77,7 +77,7 @@ class BaseSoC(SoCCore): # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: self.submodules.ddrphy = usddrphy.USDDRPHY( - pads = PHYPadsReducer(platform.request("ddram"), [0, 1]), + pads = PHYPadsReducer(platform.request("ddram"), [0, 1, 2, 3]), memtype = "DDR3", sys_clk_freq = sys_clk_freq, iodelay_clk_freq = 200e6)