diff --git a/litex_boards/platforms/digilent_genesys2.py b/litex_boards/platforms/digilent_genesys2.py
index 985c93d..6851ecd 100644
--- a/litex_boards/platforms/digilent_genesys2.py
+++ b/litex_boards/platforms/digilent_genesys2.py
@@ -149,6 +149,17 @@ _connectors = [
         "GBTCLK0_M2C_N": "L7",
         }
     ),
+    ("pmodc", {
+        "pmodc1":     "AC26",
+        "pmodc2":     "AJ27",
+        "pmodc3":     "AH30",
+        "pmodc4":     "AK29",
+        "pmodc5":     "AD26",
+        "pmodc6":     "AG30",
+        "pmodc7":     "AK30",
+        "pmodc8":     "AK28",
+        }
+    ),
 ]
 
 # Platform -----------------------------------------------------------------------------------------
diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py
index 3e989c4..5e10c7b 100755
--- a/litex_boards/targets/digilent_arty.py
+++ b/litex_boards/targets/digilent_arty.py
@@ -31,6 +31,8 @@ from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.mii import LiteEthPHYMII
+from litex.build.generic_platform import Subsignal, Pins, IOStandard
+from ctucan import CTUCAN, CTUCANWishboneWrapper
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -182,6 +184,14 @@ class BaseSoC(SoCCore):
                 with_irq = self.irq.enabled
             )
 
+def can_io():
+    return [(
+        "can",
+        0,
+        Subsignal("rx", Pins("ck_io:ck_io0")),
+        Subsignal("tx", Pins("ck_io:ck_io1")),
+        IOStandard("LVCMOS33"),
+    )]
 # Build --------------------------------------------------------------------------------------------
 
 def main():
@@ -204,6 +214,7 @@ def main():
     parser.add_target_argument("--sdcard-adapter",                            help="SDCard PMOD adapter (digilent or numato).")
     parser.add_target_argument("--with-spi-flash", action="store_true",       help="Enable SPI Flash (MMAPed).")
     parser.add_target_argument("--with-pmod-gpio", action="store_true",       help="Enable GPIOs through PMOD.") # FIXME: Temporary test.
+    parser.add_target_argument("--with-ctucan", action="store_true", help="Enable CTUCAN.")
     args = parser.parse_args()
 
     assert not (args.with_etherbone and args.eth_dynamic_ip)
@@ -222,8 +233,18 @@ def main():
         with_usb       = args.with_usb,
         with_spi_flash = args.with_spi_flash,
         with_pmod_gpio = args.with_pmod_gpio,
+        with_ctucan = args.with_ctucan,
         **parser.soc_argdict
     )
+
+    if args.with_ctucan:
+        soc.platform.add_extension(can_io())
+        can_pads = soc.platform.request("can")
+        soc.submodules.can = CTUCAN(soc.platform, can_pads, "vhdl")
+        soc.add_memory_region("can", None, soc.can.wbwrapper.size, type=[])
+        soc.add_wb_slave(soc.bus.regions["can"].origin, soc.can.wbwrapper.bus)
+        soc.add_interrupt("can")
+
     if args.sdcard_adapter == "numato":
         soc.platform.add_extension(digilent_arty._numato_sdcard_pmod_io)
     else:
diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py
index 52b507d..6953248 100755
--- a/litex_boards/targets/digilent_genesys2.py
+++ b/litex_boards/targets/digilent_genesys2.py
@@ -21,6 +21,11 @@ from litedram.modules import MT41J256M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
+from litex.build.generic_platform import Subsignal, Pins, IOStandard
+from ctucan import CTUCAN, CTUCANWishboneWrapper
+from litex.soc.integration.soc import SoCRegion
+
+
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -87,6 +92,14 @@ class BaseSoC(SoCCore):
                 pads         = platform.request_all("user_led"),
                 sys_clk_freq = sys_clk_freq)
 
+def can_io():
+    return [(
+        "can",
+        0,
+        Subsignal("rx", Pins("pmodc:pmodc1")),
+        Subsignal("tx", Pins("pmodc:pmodc2")),
+        IOStandard("LVCMOS33"),
+    )]
 # Build --------------------------------------------------------------------------------------------
 
 def main():
@@ -99,14 +112,25 @@ def main():
     sdopts = parser.target_group.add_mutually_exclusive_group()
     sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
     sdopts.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support.")
+    parser.add_target_argument("--with-ctucan", action="store_true", help="Enable CTUCAN.")
     args = parser.parse_args()
 
     soc = BaseSoC(
         sys_clk_freq   = args.sys_clk_freq,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
+        with_ctucan = args.with_ctucan,
         **parser.soc_argdict
     )
+
+    if args.with_ctucan:
+        soc.platform.add_extension(can_io())
+        can_pads = soc.platform.request("can")
+        soc.submodules.can = CTUCAN(soc.platform, can_pads, "vhdl")
+        can_region = SoCRegion(origin=soc.mem_map.get("can", None), size=soc.can.wbwrapper.size, cached=False)
+        soc.bus.add_slave(name="can", slave=soc.can.wbwrapper.bus, region=can_region)
+        soc.irq.add("can")
+
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()
     if args.with_sdcard: