diff --git a/litex_boards/platforms/pano_logic_g2.py b/litex_boards/platforms/pano_logic_g2.py
index e7d07ce..b6b2757 100755
--- a/litex_boards/platforms/pano_logic_g2.py
+++ b/litex_boards/platforms/pano_logic_g2.py
@@ -16,7 +16,7 @@ from litex.build.openocd import OpenOCD
_io = [
# clock / reset
("clk125", 0, Pins("Y13"), IOStandard("LVCMOS33")),
- ("cpu_reset", 0, Pins("AB14"), IOStandard("LVCMOS33")),
+ ("rst_n", 0, Pins("AB14"), IOStandard("LVCMOS33")),
# led
("user_led", 0, Pins("E12"), IOStandard("LVCMOS33")),
@@ -24,7 +24,7 @@ _io = [
("user_led", 2, Pins("F13"), IOStandard("LVCMOS33")),
# btn
- ("user_sw", 0, Pins("H12"), IOStandard("LVCMOS33")),
+ ("user_btn_n", 0, Pins("H12"), IOStandard("LVCMOS33")),
# serial
("serial", 0, # hdmi
@@ -98,9 +98,30 @@ _io = [
Subsignal("cke", Pins("D2"), IOStandard("SSTL18_II")),
Subsignal("odt", Pins("J6"), IOStandard("SSTL18_II")),
),
- # Ethernet phy reset (clk125 is 25 Mhz instead of 125 Mhz if reset is active)
- # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
- ("gmii_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
+
+ # ethernet
+ ("eth_rst_n", 0, Pins("R11"), IOStandard("LVCMOS33")),
+ ("eth_clocks", 0,
+ Subsignal("tx", Pins("Y11")),
+ Subsignal("gtx", Pins("AA12")),
+ Subsignal("rx", Pins("AB11")),
+ IOStandard("LVCMOS33")
+ ),
+ ("eth", 0,
+ Subsignal("rst_n", Pins("R11")),
+ Subsignal("int_n", Pins("AA4")),
+ Subsignal("mdio", Pins("AA2")),
+ Subsignal("mdc", Pins("AB6")),
+ Subsignal("rx_dv", Pins("Y7")),
+ Subsignal("rx_er", Pins("Y8")),
+ Subsignal("rx_data", Pins("Y3 Y4 R9 R7 V9 R8 U9 Y9")),
+ Subsignal("tx_en", Pins("AA8")),
+ Subsignal("tx_er", Pins("AB8")),
+ Subsignal("tx_data", Pins("AB2 AB3 AB4 AB7 AB9 AB10 T7 Y10")),
+ Subsignal("col", Pins("V7")),
+ Subsignal("crs", Pins("W4")),
+ IOStandard("LVCMOS33")
+ ),
]
diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py
index 7e1985f..1907e83 100755
--- a/litex_boards/targets/pano_logic_g2.py
+++ b/litex_boards/targets/pano_logic_g2.py
@@ -16,33 +16,59 @@ from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import *
from litex.soc.cores.led import LedChaser
+from liteeth.phy import LiteEthPHYGMII
+
# CRG ----------------------------------------------------------------------------------------------
class _CRG(Module):
- def __init__(self, platform, clk_freq):
+ def __init__(self, platform, clk_freq, with_ethernet=False):
self.clock_domains.cd_sys = ClockDomain()
# # #
- # Take Ethernet PHY out of reset to enable clk125 (25MHz otherwise).
- gmii_rst_n = platform.request("gmii_rst_n")
- self.comb += gmii_rst_n.eq(1)
+ if not with_ethernet:
+ # Take Ethernet PHY out of reset to enable 125MHz on clk125 (25MHz otherwise).
+ # See https://github.com/tomverbeure/panologic-g2#fpga-external-clocking-architecture
+ self.comb += platform.request("eth_rst_n").eq(1)
self.submodules.pll = pll = S6PLL(speedgrade=-2)
+ self.comb += pll.reset.eq(~platform.request("user_btn_n"))
pll.register_clkin(platform.request("clk125"), 125e6)
pll.create_clkout(self.cd_sys, clk_freq)
# BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore):
- def __init__(self, revision, sys_clk_freq=int(50e6), **kwargs):
+ def __init__(self, revision, sys_clk_freq=int(50e6), with_ethernet=False, with_etherbone=False, **kwargs):
platform = pano_logic_g2.Platform(revision=revision)
+ if with_etherbone:
+ sys_clk_freq = int(125e6)
# SoCCore ----------------------------------------------------------------------------------
SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
# CRG --------------------------------------------------------------------------------------
- self.submodules.crg = _CRG(platform, sys_clk_freq)
+ self.submodules.crg = _CRG(platform, sys_clk_freq, with_ethernet=with_ethernet or with_etherbone)
+
+ # Ethernet ---------------------------------------------------------------------------------
+ if with_ethernet:
+ self.submodules.ethphy = LiteEthPHYGMII(
+ clock_pads = self.platform.request("eth_clocks"),
+ pads = self.platform.request("eth"),
+ with_hw_init_reset = False)
+ platform.add_platform_command("""NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE;""")
+ self.add_csr("ethphy")
+ self.add_ethernet(phy=self.ethphy)
+
+ # Etherbone --------------------------------------------------------------------------------
+ if with_etherbone:
+ self.submodules.ethphy = LiteEthPHYGMII(
+ clock_pads = self.platform.request("eth_clocks"),
+ pads = self.platform.request("eth"),
+ with_hw_init_reset = False)
+ platform.add_platform_command("""NET "eth_clocks_rx" CLOCK_DEDICATED_ROUTE = FALSE;""")
+ self.add_csr("ethphy")
+ self.add_etherbone(phy=self.ethphy)
# Leds -------------------------------------------------------------------------------------
self.submodules.leds = LedChaser(
@@ -59,9 +85,16 @@ def main():
parser.add_argument("--revision", default="c", help="Board revision c (default) or b")
builder_args(parser)
soc_core_args(parser)
+ parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+ parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
args = parser.parse_args()
- soc = BaseSoC(revision=args.revision, **soc_core_argdict(args))
+ assert not (args.with_ethernet and args.with_etherbone)
+ soc = BaseSoC(
+ revision = args.revision,
+ with_ethernet = args.with_ethernet,
+ with_etherbone = args.with_etherbone,
+ **soc_core_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=args.build)