From 302e4ffdffbd1516e987833b0422a5d3e20f81a5 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 12 Nov 2020 13:34:43 +0100 Subject: [PATCH] targets/simple: simplify (only keep minimal SoC + Leds) and add load argument. ex of use: ./simple.py litex_boards.platform.ulx3s --build --load ./simple.py litex_boards.platform.trellisboard --build --load ./simple.py litex_boards.platform.arty --build --load etc... --- litex_boards/targets/simple.py | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 29eea19..99e8b07 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -3,7 +3,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2014-2019 Florent Kermarrec +# Copyright (c) 2014-2020 Florent Kermarrec # Copyright (c) 2013-2014 Sebastien Bourdeauducq # SPDX-License-Identifier: BSD-2-Clause @@ -18,7 +18,7 @@ from litex.build.io import CRG from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * -from liteeth.phy import LiteEthPHY +from litex.soc.cores.led import LedChaser # BaseSoC ------------------------------------------------------------------------------------------ @@ -35,14 +35,11 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) - # Ethernet --------------------------------------------------------------------------------- - if with_ethernet: - self.submodules.ethphy = LiteEthPHY( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth"), - clk_freq = self.clk_freq) - self.add_csr("ethphy") - self.add_ethernet(phy=self.ethphy) + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") # Build -------------------------------------------------------------------------------------------- @@ -50,21 +47,24 @@ def main(): parser = argparse.ArgumentParser(description="Generic LiteX SoC") parser.add_argument("platform", help="Module name of the platform to build for") parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--toolchain", default=None, help="FPGA toolchain (None default)") builder_args(parser) soc_core_args(parser) args = parser.parse_args() platform_module = importlib.import_module(args.platform) + platform_kwargs = {} if args.toolchain is not None: - platform = platform_module.Platform(toolchain=args.toolchain) - else: - platform = platform_module.Platform() - soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) + platform_kwargs["toolchain"] = args.toolchain + platform = platform_module.Platform(**platform_kwargs) + soc = BaseSoC(platform,**soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(run=args.build) + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + platform.bitstream_ext)) if __name__ == "__main__": main()