From 30ea463b41a5beddab50d0f8575e3ed17e44652d Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 6 Dec 2019 16:01:53 +0100 Subject: [PATCH] targets: keep attributes are no longer needed since automatically added when applying constraints to signals. --- litex_boards/community/targets/ac701.py | 6 ------ litex_boards/community/targets/de10lite.py | 4 ---- litex_boards/community/targets/de1soc.py | 4 ---- litex_boards/community/targets/de2_115.py | 4 ---- litex_boards/community/targets/ecp5_evn.py | 2 -- litex_boards/official/targets/arty.py | 6 ------ litex_boards/official/targets/de0nano.py | 4 ---- litex_boards/official/targets/genesys2.py | 5 ----- litex_boards/official/targets/kc705.py | 5 ----- litex_boards/official/targets/kcu105.py | 5 ----- litex_boards/official/targets/minispartan6.py | 3 --- litex_boards/official/targets/nexys4ddr.py | 6 ------ litex_boards/official/targets/nexys_video.py | 6 ------ litex_boards/official/targets/versa_ecp5.py | 8 -------- 14 files changed, 68 deletions(-) diff --git a/litex_boards/community/targets/ac701.py b/litex_boards/community/targets/ac701.py index 16d521d..20ec80f 100755 --- a/litex_boards/community/targets/ac701.py +++ b/litex_boards/community/targets/ac701.py @@ -34,10 +34,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -92,8 +88,6 @@ class EthernetSoC(BaseSoC): self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/community/targets/de10lite.py b/litex_boards/community/targets/de10lite.py index 468dc60..30765b3 100755 --- a/litex_boards/community/targets/de10lite.py +++ b/litex_boards/community/targets/de10lite.py @@ -25,10 +25,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - # power on rst rst_n = Signal() self.sync.por += rst_n.eq(1) diff --git a/litex_boards/community/targets/de1soc.py b/litex_boards/community/targets/de1soc.py index 22572a2..634a2e1 100755 --- a/litex_boards/community/targets/de1soc.py +++ b/litex_boards/community/targets/de1soc.py @@ -25,10 +25,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - # power on rst rst_n = Signal() self.sync.por += rst_n.eq(1) diff --git a/litex_boards/community/targets/de2_115.py b/litex_boards/community/targets/de2_115.py index 5749d34..6a735c2 100755 --- a/litex_boards/community/targets/de2_115.py +++ b/litex_boards/community/targets/de2_115.py @@ -25,10 +25,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - # power on rst rst_n = Signal() self.sync.por += rst_n.eq(1) diff --git a/litex_boards/community/targets/ecp5_evn.py b/litex_boards/community/targets/ecp5_evn.py index ca62838..fc1f5af 100755 --- a/litex_boards/community/targets/ecp5_evn.py +++ b/litex_boards/community/targets/ecp5_evn.py @@ -22,8 +22,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - # clk / rst clk = clk12 = platform.request("clk12") rst_n = platform.request("rst_n") diff --git a/litex_boards/official/targets/arty.py b/litex_boards/official/targets/arty.py index 9f15097..1593db3 100755 --- a/litex_boards/official/targets/arty.py +++ b/litex_boards/official/targets/arty.py @@ -32,10 +32,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -97,8 +93,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/de0nano.py b/litex_boards/official/targets/de0nano.py index 6033591..bacfc69 100755 --- a/litex_boards/official/targets/de0nano.py +++ b/litex_boards/official/targets/de0nano.py @@ -25,10 +25,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - # Power on reset rst_n = Signal() self.sync.por += rst_n.eq(1) diff --git a/litex_boards/official/targets/genesys2.py b/litex_boards/official/targets/genesys2.py index d37e1c1..ecad089 100755 --- a/litex_boards/official/targets/genesys2.py +++ b/litex_boards/official/targets/genesys2.py @@ -29,9 +29,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(~platform.request("cpu_reset_n")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -87,8 +84,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/kc705.py b/litex_boards/official/targets/kc705.py index e221afc..8746080 100755 --- a/litex_boards/official/targets/kc705.py +++ b/litex_boards/official/targets/kc705.py @@ -31,9 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) pll.register_clkin(platform.request("clk200"), 200e6) @@ -91,8 +88,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/kcu105.py b/litex_boards/official/targets/kcu105.py index 9a3a2b7..ec36e9d 100755 --- a/litex_boards/official/targets/kcu105.py +++ b/litex_boards/official/targets/kcu105.py @@ -30,9 +30,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.submodules.pll = pll = USMMCM(speedgrade=-2) self.comb += pll.reset.eq(platform.request("cpu_reset")) self.clock_domains.cd_pll4x = ClockDomain(reset_less=True) @@ -127,8 +124,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.cd_eth_rx.clk.attr.add("keep") - self.ethphy.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/minispartan6.py b/litex_boards/official/targets/minispartan6.py index e317960..917baee 100755 --- a/litex_boards/official/targets/minispartan6.py +++ b/litex_boards/official/targets/minispartan6.py @@ -29,9 +29,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys_ps.clk.attr.add("keep") - self.submodules.pll = pll = S6PLL(speedgrade=-1) pll.register_clkin(platform.request("clk32"), 32e6) pll.create_clkout(self.cd_sys, clk_freq) diff --git a/litex_boards/official/targets/nexys4ddr.py b/litex_boards/official/targets/nexys4ddr.py index 0d9f8e1..fdb48c4 100755 --- a/litex_boards/official/targets/nexys4ddr.py +++ b/litex_boards/official/targets/nexys4ddr.py @@ -31,10 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys2x.clk.attr.add("keep") - self.cd_sys2x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -95,8 +91,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/nexys_video.py b/litex_boards/official/targets/nexys_video.py index 036f8e5..efbc0d7 100755 --- a/litex_boards/official/targets/nexys_video.py +++ b/litex_boards/official/targets/nexys_video.py @@ -31,10 +31,6 @@ class _CRG(Module): # # # - self.cd_sys.clk.attr.add("keep") - self.cd_sys4x.clk.attr.add("keep") - self.cd_sys4x_dqs.clk.attr.add("keep") - self.submodules.pll = pll = S7MMCM(speedgrade=-1) self.comb += pll.reset.eq(~platform.request("cpu_reset")) pll.register_clkin(platform.request("clk100"), 100e6) @@ -94,8 +90,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex_boards/official/targets/versa_ecp5.py b/litex_boards/official/targets/versa_ecp5.py index 45b59c0..1e7ffa9 100755 --- a/litex_boards/official/targets/versa_ecp5.py +++ b/litex_boards/official/targets/versa_ecp5.py @@ -35,12 +35,6 @@ class _CRG(Module): # # # - self.cd_init.clk.attr.add("keep") - self.cd_por.clk.attr.add("keep") - self.cd_sys.clk.attr.add("keep") - self.cd_sys2x.clk.attr.add("keep") - self.cd_sys2x_i.clk.attr.add("keep") - self.stop = Signal() # clk / rst @@ -124,8 +118,6 @@ class EthernetSoC(BaseSoC): self.add_csr("ethmac") self.add_interrupt("ethmac") - self.ethphy.crg.cd_eth_rx.clk.attr.add("keep") - self.ethphy.crg.cd_eth_tx.clk.attr.add("keep") self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)