From 313e758ffeb79290ea072601baa0eb68ce95566a Mon Sep 17 00:00:00 2001 From: AEW2015 Date: Fri, 3 Jun 2022 20:49:52 -0600 Subject: [PATCH] Updated copywrite and renamed to avnet_aesku40 --- README.md | 1 + .../platforms/{xilinx_aesku40.py => avnet_aesku40.py} | 2 +- .../targets/{xilinx_aesku40.py => avnet_aesku40.py} | 6 +++--- 3 files changed, 5 insertions(+), 4 deletions(-) rename litex_boards/platforms/{xilinx_aesku40.py => avnet_aesku40.py} (99%) rename litex_boards/targets/{xilinx_aesku40.py => avnet_aesku40.py} (97%) diff --git a/README.md b/README.md index 8a30d7b..58839fe 100644 --- a/README.md +++ b/README.md @@ -105,6 +105,7 @@ Some of the suported boards, see yours? Give LiteX-Boards a try! ├── antmicro_lpddr4_test_board ├── arduino_mkrvidor4000 ├── avalanche + ├── avnet_aesku40 ├── berkeleylab_marblemini ├── berkeleylab_marble ├── camlink_4k diff --git a/litex_boards/platforms/xilinx_aesku40.py b/litex_boards/platforms/avnet_aesku40.py similarity index 99% rename from litex_boards/platforms/xilinx_aesku40.py rename to litex_boards/platforms/avnet_aesku40.py index d6f3a1f..71b7edc 100644 --- a/litex_boards/platforms/xilinx_aesku40.py +++ b/litex_boards/platforms/avnet_aesku40.py @@ -1,7 +1,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2017-2019 Florent Kermarrec +# Copyright (c) 2022 Andrew Elbert Wilson # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * diff --git a/litex_boards/targets/xilinx_aesku40.py b/litex_boards/targets/avnet_aesku40.py similarity index 97% rename from litex_boards/targets/xilinx_aesku40.py rename to litex_boards/targets/avnet_aesku40.py index 0d8d01a..1c0ec9f 100755 --- a/litex_boards/targets/xilinx_aesku40.py +++ b/litex_boards/targets/avnet_aesku40.py @@ -3,7 +3,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2018-2020 Florent Kermarrec +# Copyright (c) 2022 Andrew Elbert Wilson # SPDX-License-Identifier: BSD-2-Clause import os @@ -12,7 +12,7 @@ import argparse from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer -from litex_boards.platforms import aesku40 +from litex_boards.platforms import avnet_aesku40 from litex.soc.cores.clock import * from litex.soc.integration.soc_core import * @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", with_led_chaser=True, with_pcie=False, with_sata=False, **kwargs): - platform = aesku40.Platform() + platform = avnet_aesku40.Platform() # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq,