From 31c680abf8a9201e01d23c2e55ba794ebea2f6b6 Mon Sep 17 00:00:00 2001 From: Charles-Henri Mousset Date: Sun, 30 Apr 2023 09:42:31 +0200 Subject: [PATCH] [enh] added option for uartbone --- litex_boards/platforms/colorlight_i5a_907.py | 7 ++++--- litex_boards/targets/colorlight_5a_75x.py | 17 +++++++++++++++-- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/litex_boards/platforms/colorlight_i5a_907.py b/litex_boards/platforms/colorlight_i5a_907.py index 7d93f3a..8c7d08c 100644 --- a/litex_boards/platforms/colorlight_i5a_907.py +++ b/litex_boards/platforms/colorlight_i5a_907.py @@ -7,7 +7,7 @@ # The Colorlight 5A-75B PCB and IOs have been documented by @miek and @smunaut: # https://github.com/q3k/chubby75/tree/master/5a-75b -# The Colorlight 5A-907 PCB, which is heavily based on the 5A-75B has been documented by @chmouss: +# The Colorlight 5A-907 PCB, which is heavily based on the 5A-75B, has been documented by @chmouss: # https://github.com/chmousset/colorlight_reverse @@ -108,7 +108,8 @@ _io_v7_0 = [ # Documented by @miek and @chmouss # To use the USB: # shunt R124 and R134 # remove R107 - # connect on R107's pad towards FPGA to R124 shunt through a 1.5k resistor + # connect R107's pad towards FPGA to R124 shunt through a 1.5k resistor + # note: it conflicts with uartbone ("usb", 0, Subsignal("d_p", Pins("F15")), # EXT_VOL pin 1 Subsignal("d_n", Pins("E16")), # EXT_VOL pin 2 @@ -138,7 +139,7 @@ class Platform(LatticeECP5Platform): default_clk_period = 1e9/25e6 def __init__(self, revision="7.0", toolchain="trellis"): - assert revision in ["6.1", "7.0", "8.0"] + assert revision in ["7.0"] self.revision = revision device = {"7.0": "LFE5U-25F-6BG256C"}[revision] io = {"7.0": _io_v7_0 }[revision] diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 1a95470..d2dc769 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -39,6 +39,10 @@ # Disclaimer: SoC 2) is still a Proof of Concept with large timings violations on the IP/UDP and # Etherbone stack that need to be optimized. It was initially just used to validate the reversed # pinout but happens to work on hardware... +# +# Note you can also use the i5a-907 board: +# ./colorlight_5a_75x.py --board=i5a-907 --revision=7.0 --build + from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer @@ -118,6 +122,7 @@ class BaseSoC(SoCCore): def __init__(self, board, revision, sys_clk_freq=60e6, toolchain="trellis", with_ethernet = False, with_etherbone = False, + with_uartbone = False, eth_ip = "192.168.1.50", eth_phy = 0, with_led_chaser = True, @@ -180,12 +185,18 @@ class BaseSoC(SoCCore): # Leds ------------------------------------------------------------------------------------- # Disable leds when serial is used. - if platform.lookup_request("serial", loose=True) is None and with_led_chaser or board == "i5a-907": + if (platform.lookup_request("serial", loose=True) is None and with_led_chaser + or board == "i5a-907"): self.leds = LedChaser( pads = platform.request_all("user_led_n"), sys_clk_freq = sys_clk_freq) - self.add_uartbone(name="uartbone") + # Uartbone --------------------------------------------------------------------------------- + if with_uartbone: + if board != "i5a-907": + raise ValueError("uartbone only supported on i5a-907") + self.add_uartbone(name="uartbone") + # Build -------------------------------------------------------------------------------------------- @@ -198,6 +209,7 @@ def main(): ethopts = parser.target_group.add_mutually_exclusive_group() ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") + parser.add_target_argument("--with-uartbone", action="store_true", help="Add uartbone on 'FAN OUT' connector.") parser.add_target_argument("--eth-ip", default="192.168.1.50", help="Ethernet/Etherbone IP address.") parser.add_target_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).") parser.add_target_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.") @@ -209,6 +221,7 @@ def main(): toolchain = args.toolchain, with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, + with_uartbone = args.with_uartbone, eth_ip = args.eth_ip, eth_phy = args.eth_phy, use_internal_osc = args.use_internal_osc,