From 1b1ed5ebf1f2dbdbdbf9941cfd26977cb1a75a3f Mon Sep 17 00:00:00 2001 From: Basel Sayeh Date: Thu, 12 Nov 2020 01:56:36 +0200 Subject: [PATCH 1/2] add Qmtech EP4CE15 coreboard support --- litex_boards/platforms/qmtech_EP4CE15.py | 89 ++++++++++++++++++ litex_boards/targets/qmtech_EP4CE15.py | 115 +++++++++++++++++++++++ 2 files changed, 204 insertions(+) create mode 100644 litex_boards/platforms/qmtech_EP4CE15.py create mode 100755 litex_boards/targets/qmtech_EP4CE15.py diff --git a/litex_boards/platforms/qmtech_EP4CE15.py b/litex_boards/platforms/qmtech_EP4CE15.py new file mode 100644 index 0000000..3be238b --- /dev/null +++ b/litex_boards/platforms/qmtech_EP4CE15.py @@ -0,0 +1,89 @@ +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2014-2019 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +from litex.build.generic_platform import * +from litex.build.altera import AlteraPlatform +from litex.build.altera.programmer import USBBlaster + +# IOs ---------------------------------------------------------------------------------------------- + +_io = [ + # Clk + ("clk50", 0, Pins("T2"), IOStandard("3.3-V LVTTL")), + + # Leds + ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")), + + # Button + ("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")), + ("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")), + + # Serial + ("serial", 0, + # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) + Subsignal("tx", Pins("AA13"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10) + Subsignal("rx", Pins("AA14"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) + ), + + # SDR SDRAM + ("sdram_clock", 0, Pins("Y6"), IOStandard("3.3-V LVTTL")), + ("sdram", 0, + Subsignal("a", Pins( + "V2 V1 U2 U1 V3 V4 Y2 AA1", + "Y3 V5 W1 Y4 V6")), + Subsignal("ba", Pins("Y1 W2")), + Subsignal("cs_n", Pins("AA3")), + Subsignal("cke", Pins("W6")), + Subsignal("ras_n", Pins("AB3")), + Subsignal("cas_n", Pins("AA4")), + Subsignal("we_n", Pins("AB4")), + Subsignal("dq", Pins( + "AA10 AB9 AA9 AB8 AA8 AB7 AA7 AB5", + "Y7 W8 Y8 V9 V10 Y10 W10 V11")), + Subsignal("dm", Pins("AA5 W7")), + IOStandard("3.3-V LVTTL") + ), + + # GPIOs + #ignore for now + #("gpio_0", 0, Pins( + # "D3 C3 A2 A3 B3 B4 A4 B5", + # "A5 D5 B6 A6 B7 D6 A7 C6", + # "C8 E6 E7 D8 E8 F8 F9 E9", + # "C9 D9 E11 E10 C11 B11 A12 D11", + # "D12 B12"), + # IOStandard("3.3-V LVTTL") + #), + #("gpio_1", 0, Pins( + # "F13 T15 T14 T13 R13 T12 R12 T11", + # "T10 R11 P11 R10 N12 P9 N9 N11", + # "L16 K16 R16 L15 P15 P16 R14 N16", + # "N15 P14 L14 N14 M10 L13 J16 K15", + # "J13 J14"), + # IOStandard("3.3-V LVTTL") + #), + #("gpio_2", 0, Pins( + # "A14 B16 C14 C16 C15 D16 D15 D14", + # "F15 F16 F14 G16 G15"), + # IOStandard("3.3-V LVTTL") + #), +] + +# Platform ----------------------------------------------------------------------------------------- + +class Platform(AlteraPlatform): + default_clk_name = "clk50" + default_clk_period = 1e9/50e6 + + def __init__(self): + AlteraPlatform.__init__(self, "EP4CE15F23C8", _io) + + def create_programmer(self): + return USBBlaster() + + def do_finalize(self, fragment): + AlteraPlatform.do_finalize(self, fragment) + self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) diff --git a/litex_boards/targets/qmtech_EP4CE15.py b/litex_boards/targets/qmtech_EP4CE15.py new file mode 100755 index 0000000..2cfa371 --- /dev/null +++ b/litex_boards/targets/qmtech_EP4CE15.py @@ -0,0 +1,115 @@ +#!/usr/bin/env python3 + +# +# This file is part of LiteX-Boards. +# +# Copyright (c) 2015-2020 Florent Kermarrec +# SPDX-License-Identifier: BSD-2-Clause + +import os +import argparse + +from migen import * +from migen.genlib.resetsync import AsyncResetSynchronizer + +from litex.build.io import DDROutput + +from litex_boards.platforms import qmtech_EP4CE15 + +from litex.soc.cores.clock import CycloneIVPLL +from litex.soc.integration.soc_core import * +from litex.soc.integration.soc_sdram import * +from litex.soc.integration.builder import * +from litex.soc.cores.led import LedChaser + +from litedram.modules import IS42S16160 +from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq, sdram_rate="1:1"): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + if sdram_rate == "1:2": + self.clock_domains.cd_sys2x = ClockDomain() + self.clock_domains.cd_sys2x_ps = ClockDomain(reset_less=True) + else: + self.clock_domains.cd_sys_ps = ClockDomain(reset_less=True) + + # # # + + # Clk / Rst + clk50 = platform.request("clk50") + + # PLL + self.submodules.pll = pll = CycloneIVPLL(speedgrade="-6") + self.comb += pll.reset.eq(self.rst) + pll.register_clkin(clk50, 50e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + if sdram_rate == "1:2": + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased. + else: + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + + # SDRAM clock + sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps") + self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk) + +# BaseSoC ------------------------------------------------------------------------------------------ + +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(50e6), sdram_rate="1:1", **kwargs): + platform = qmtech_EP4CE15.Platform() + + # SoCCore ---------------------------------------------------------------------------------- + SoCCore.__init__(self, platform, sys_clk_freq, + ident = "LiteX SoC on qmtech_EP4CE15", + ident_version = True, + **kwargs) + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate=sdram_rate) + + # SDR SDRAM -------------------------------------------------------------------------------- + if not self.integrated_main_ram_size: + sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY + self.submodules.sdrphy = sdrphy_cls(platform.request("sdram")) + self.add_sdram("sdram", + phy = self.sdrphy, + module = IS42S16160(sys_clk_freq, sdram_rate), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all("user_led"), + sys_clk_freq = sys_clk_freq) + self.add_csr("leds") + +# Build -------------------------------------------------------------------------------------------- + +def main(): + parser = argparse.ArgumentParser(description="LiteX SoC on qmtech_EP4CE15") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate") + builder_args(parser) + soc_sdram_args(parser) + args = parser.parse_args() + + soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args)) + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + + if args.load: + prog = soc.platform.create_programmer() + prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".sof")) + +if __name__ == "__main__": + main() From 0fc67ddfdb636ce2ede6f540b6549180ead10b71 Mon Sep 17 00:00:00 2001 From: Basel Sayeh Date: Thu, 12 Nov 2020 15:25:39 +0200 Subject: [PATCH 2/2] update copyright --- litex_boards/platforms/qmtech_EP4CE15.py | 2 +- litex_boards/targets/qmtech_EP4CE15.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/litex_boards/platforms/qmtech_EP4CE15.py b/litex_boards/platforms/qmtech_EP4CE15.py index 3be238b..33ac6c3 100644 --- a/litex_boards/platforms/qmtech_EP4CE15.py +++ b/litex_boards/platforms/qmtech_EP4CE15.py @@ -1,7 +1,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2014-2019 Florent Kermarrec +# Copyright (c) 2020 Basel Sayeh # SPDX-License-Identifier: BSD-2-Clause from litex.build.generic_platform import * diff --git a/litex_boards/targets/qmtech_EP4CE15.py b/litex_boards/targets/qmtech_EP4CE15.py index 2cfa371..b773662 100755 --- a/litex_boards/targets/qmtech_EP4CE15.py +++ b/litex_boards/targets/qmtech_EP4CE15.py @@ -3,7 +3,7 @@ # # This file is part of LiteX-Boards. # -# Copyright (c) 2015-2020 Florent Kermarrec +# Copyright (c) 2020 Basel Sayeh # SPDX-License-Identifier: BSD-2-Clause import os