From 33b0400aed523037d406e2b97f327ffa5500865c Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 6 Nov 2022 21:39:52 +0100 Subject: [PATCH] targets: Update LiteXArgumentParser imports. --- litex_boards/targets/adi_adrv2crr_fmc.py | 2 +- litex_boards/targets/adi_plutosdr.py | 2 +- litex_boards/targets/alchitry_au.py | 2 +- litex_boards/targets/alchitry_mojo.py | 2 +- litex_boards/targets/aliexpress_xc7k420t.py | 2 +- litex_boards/targets/alinx_ax7010.py | 2 +- litex_boards/targets/alinx_axu2cga.py | 2 +- litex_boards/targets/antmicro_artix_dc_scm.py | 2 +- litex_boards/targets/antmicro_datacenter_ddr4_test_board.py | 2 +- litex_boards/targets/antmicro_lpddr4_test_board.py | 2 +- litex_boards/targets/berkeleylab_marble.py | 2 +- litex_boards/targets/camlink_4k.py | 2 +- litex_boards/targets/colorlight_5a_75x.py | 2 +- litex_boards/targets/colorlight_i5.py | 2 +- litex_boards/targets/decklink_intensity_pro_4k.py | 2 +- litex_boards/targets/decklink_mini_4k.py | 2 +- litex_boards/targets/decklink_quad_hdmi_recorder.py | 2 +- litex_boards/targets/digilent_arty.py | 2 +- litex_boards/targets/digilent_arty_s7.py | 2 +- litex_boards/targets/digilent_arty_z7.py | 2 +- litex_boards/targets/digilent_atlys.py | 2 +- litex_boards/targets/digilent_basys3.py | 2 +- litex_boards/targets/digilent_cmod_a7.py | 2 +- litex_boards/targets/digilent_genesys2.py | 2 +- litex_boards/targets/digilent_nexys4.py | 2 +- litex_boards/targets/digilent_nexys4ddr.py | 2 +- litex_boards/targets/digilent_nexys_video.py | 2 +- litex_boards/targets/digilent_pynq_z1.py | 2 +- litex_boards/targets/digilent_zedboard.py | 2 +- litex_boards/targets/ebaz4205.py | 2 +- litex_boards/targets/efinix_t8f81_dev_kit.py | 2 +- litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py | 2 +- litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py | 2 +- litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py | 2 +- litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py | 2 +- litex_boards/targets/efinix_xyloni_dev_kit.py | 2 +- litex_boards/targets/ego1.py | 2 +- litex_boards/targets/enclustra_mercury_kx2.py | 2 +- litex_boards/targets/enclustra_mercury_xu5.py | 2 +- litex_boards/targets/fairwaves_xtrx.py | 2 +- litex_boards/targets/fpc_iii.py | 2 +- litex_boards/targets/fpgawars_alhambra2.py | 2 +- litex_boards/targets/gsd_butterstick.py | 2 +- litex_boards/targets/gsd_orangecrab.py | 2 +- litex_boards/targets/hackaday_hadbadge.py | 2 +- litex_boards/targets/hpcstore_xc7k420t.py | 2 +- litex_boards/targets/icebreaker.py | 2 +- litex_boards/targets/icebreaker_bitsy.py | 2 +- litex_boards/targets/jungle_electronics_fireant.py | 2 +- litex_boards/targets/kosagi_fomu.py | 2 +- litex_boards/targets/kosagi_netv2.py | 2 +- litex_boards/targets/krtkl_snickerdoodle.py | 2 +- litex_boards/targets/lambdaconcept_ecpix5.py | 2 +- litex_boards/targets/lattice_crosslink_nx_evn.py | 2 +- litex_boards/targets/lattice_crosslink_nx_vip.py | 2 +- litex_boards/targets/lattice_ecp5_evn.py | 2 +- litex_boards/targets/lattice_ecp5_vip.py | 2 +- litex_boards/targets/lattice_ice40up5k_evn.py | 2 +- litex_boards/targets/lattice_versa_ecp5.py | 2 +- litex_boards/targets/limesdr_mini_v2.py | 2 +- litex_boards/targets/linsn_rv901t.py | 2 +- litex_boards/targets/litex_acorn_baseboard.py | 2 +- litex_boards/targets/logicbone.py | 2 +- litex_boards/targets/machdyne_schoko.py | 2 +- litex_boards/targets/micronova_mercury2.py | 2 +- litex_boards/targets/mist.py | 2 +- litex_boards/targets/mnt_rkx7.py | 2 +- litex_boards/targets/muselab_icesugar.py | 2 +- litex_boards/targets/muselab_icesugar_pro.py | 2 +- litex_boards/targets/myminieye_runber.py | 2 +- litex_boards/targets/newae_cw305.py | 2 +- litex_boards/targets/numato_aller.py | 2 +- litex_boards/targets/numato_mimas_a7.py | 2 +- litex_boards/targets/numato_nereid.py | 2 +- litex_boards/targets/numato_tagus.py | 2 +- litex_boards/targets/pano_logic_g2.py | 2 +- litex_boards/targets/qmtech_10cl006.py | 2 +- litex_boards/targets/qmtech_5cefa2.py | 2 +- litex_boards/targets/qmtech_ep4ce15_starter_kit.py | 2 +- litex_boards/targets/qmtech_ep4cex5.py | 2 +- litex_boards/targets/qmtech_ep4cgx150.py | 2 +- litex_boards/targets/qmtech_wukong.py | 2 +- litex_boards/targets/qmtech_xc7a35t.py | 2 +- litex_boards/targets/quicklogic_quickfeather.py | 2 +- litex_boards/targets/qwertyembedded_beaglewire.py | 2 +- litex_boards/targets/radiona_ulx3s.py | 2 +- litex_boards/targets/rcs_arctic_tern_bmc_card.py | 2 +- litex_boards/targets/redpitaya.py | 2 +- litex_boards/targets/rz_easyfpga.py | 2 +- litex_boards/targets/saanlima_pipistrello.py | 2 +- litex_boards/targets/scarabhardware_minispartan6.py | 2 +- litex_boards/targets/seeedstudio_spartan_edge_accelerator.py | 2 +- litex_boards/targets/siglent_sds1104xe.py | 2 +- litex_boards/targets/simple.py | 2 +- litex_boards/targets/sipeed_tang_nano.py | 2 +- litex_boards/targets/sipeed_tang_nano_4k.py | 2 +- litex_boards/targets/sipeed_tang_nano_9k.py | 2 +- litex_boards/targets/sipeed_tang_primer.py | 2 +- litex_boards/targets/sipeed_tang_primer_20k.py | 2 +- litex_boards/targets/sitlinv_a_e115fb.py | 2 +- litex_boards/targets/sitlinv_stlv7325.py | 2 +- litex_boards/targets/sqrl_acorn.py | 2 +- litex_boards/targets/sqrl_fk33.py | 2 +- litex_boards/targets/sqrl_xcu1525.py | 2 +- litex_boards/targets/terasic_de0nano.py | 2 +- litex_boards/targets/terasic_de10lite.py | 2 +- litex_boards/targets/terasic_de10nano.py | 2 +- litex_boards/targets/terasic_de1soc.py | 2 +- litex_boards/targets/terasic_de2_115.py | 2 +- litex_boards/targets/terasic_deca.py | 2 +- litex_boards/targets/terasic_sockit.py | 2 +- litex_boards/targets/tinyfpga_bx.py | 2 +- litex_boards/targets/trellisboard.py | 2 +- litex_boards/targets/trenz_c10lprefkit.py | 2 +- litex_boards/targets/trenz_cyc1000.py | 2 +- litex_boards/targets/trenz_max1000.py | 2 +- litex_boards/targets/trenz_te0725.py | 2 +- litex_boards/targets/trenz_tec0117.py | 2 +- litex_boards/targets/tul_pynq_z2.py | 2 +- litex_boards/targets/xilinx_ac701.py | 2 +- litex_boards/targets/xilinx_alveo_u280.py | 2 +- litex_boards/targets/xilinx_kc705.py | 2 +- litex_boards/targets/xilinx_kcu105.py | 2 +- litex_boards/targets/xilinx_kv260.py | 2 +- litex_boards/targets/xilinx_vc707.py | 2 +- litex_boards/targets/xilinx_vcu118.py | 2 +- litex_boards/targets/xilinx_zcu102.py | 2 +- litex_boards/targets/xilinx_zcu104.py | 2 +- litex_boards/targets/xilinx_zcu106.py | 2 +- litex_boards/targets/xilinx_zcu216.py | 2 +- litex_boards/targets/xilinx_zybo_z7.py | 2 +- litex_boards/targets/ztex213.py | 2 +- 132 files changed, 132 insertions(+), 132 deletions(-) diff --git a/litex_boards/targets/adi_adrv2crr_fmc.py b/litex_boards/targets/adi_adrv2crr_fmc.py index 72b7cb3..841f5b2 100755 --- a/litex_boards/targets/adi_adrv2crr_fmc.py +++ b/litex_boards/targets/adi_adrv2crr_fmc.py @@ -121,7 +121,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=adi_adrv2crr_fmc.Platform, description="LiteX SoC on ADI ADRV2CRR-FMC") parser.add_target_argument("--sys-clk-freq", default=150e6, help="System clock frequency (default: 150 MHz)") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support") diff --git a/litex_boards/targets/adi_plutosdr.py b/litex_boards/targets/adi_plutosdr.py index fdfe73c..c5e51c6 100755 --- a/litex_boards/targets/adi_plutosdr.py +++ b/litex_boards/targets/adi_plutosdr.py @@ -76,7 +76,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=adi_plutosdr.Platform, description="LiteX SoC on Pluto SDR") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/alchitry_au.py b/litex_boards/targets/alchitry_au.py index 40f5ebf..6e5800c 100755 --- a/litex_boards/targets/alchitry_au.py +++ b/litex_boards/targets/alchitry_au.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=alchitry_au.Platform, description="LiteX SoC on Alchitry Au(+)") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--variant", default="au", help="Board variant (au or au+).") diff --git a/litex_boards/targets/alchitry_mojo.py b/litex_boards/targets/alchitry_mojo.py index a7281aa..11285a5 100755 --- a/litex_boards/targets/alchitry_mojo.py +++ b/litex_boards/targets/alchitry_mojo.py @@ -143,7 +143,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=alchitry_mojo.Platform, description="LiteX SoC on Alchitry Mojo") parser.add_target_argument("--sys-clk-freq", default=62.5e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate: (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/aliexpress_xc7k420t.py b/litex_boards/targets/aliexpress_xc7k420t.py index 9988a5a..1532511 100755 --- a/litex_boards/targets/aliexpress_xc7k420t.py +++ b/litex_boards/targets/aliexpress_xc7k420t.py @@ -62,7 +62,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=aliexpress_xc7k420t.Platform, description="LiteX SoC on AliExpress u420t") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI-mode flash support.") diff --git a/litex_boards/targets/alinx_ax7010.py b/litex_boards/targets/alinx_ax7010.py index 28b1823..631cfe2 100755 --- a/litex_boards/targets/alinx_ax7010.py +++ b/litex_boards/targets/alinx_ax7010.py @@ -56,7 +56,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=alinx_ax7010.Platform, description="LiteX SoC on zynq xc7z010") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") args = parser.parse_args() diff --git a/litex_boards/targets/alinx_axu2cga.py b/litex_boards/targets/alinx_axu2cga.py index 6965295..53b03c7 100755 --- a/litex_boards/targets/alinx_axu2cga.py +++ b/litex_boards/targets/alinx_axu2cga.py @@ -172,7 +172,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=alinx_axu2cga.Platform, description="LiteX SoC on Alinx AXU2CGA") parser.add_target_argument("--cable", default="ft232", help="JTAG interface.") parser.add_target_argument("--sys-clk-freq", default=25e6, help="System clock frequency.") diff --git a/litex_boards/targets/antmicro_artix_dc_scm.py b/litex_boards/targets/antmicro_artix_dc_scm.py index 76ae019..6ac1e03 100755 --- a/litex_boards/targets/antmicro_artix_dc_scm.py +++ b/litex_boards/targets/antmicro_artix_dc_scm.py @@ -113,7 +113,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=antmicro_artix_dc_scm.Platform, description="LiteX SoC on Artix DC-SCM") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py index 8388fc8..a88a5a2 100755 --- a/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py +++ b/litex_boards/targets/antmicro_datacenter_ddr4_test_board.py @@ -178,7 +178,7 @@ class LiteDRAMSettingsEncoder(json.JSONEncoder): return super().default(o) def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=antmicro_datacenter_ddr4_test_board.Platform, description="LiteX SoC on DDR4 Datacenter Test Board") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency") diff --git a/litex_boards/targets/antmicro_lpddr4_test_board.py b/litex_boards/targets/antmicro_lpddr4_test_board.py index c627d7d..cffb31d 100755 --- a/litex_boards/targets/antmicro_lpddr4_test_board.py +++ b/litex_boards/targets/antmicro_lpddr4_test_board.py @@ -112,7 +112,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=antmicro_lpddr4_test_board.Platform, description="LiteX SoC on LPDDR4 Test Board") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") diff --git a/litex_boards/targets/berkeleylab_marble.py b/litex_boards/targets/berkeleylab_marble.py index 38f64d7..0b8f7af 100755 --- a/litex_boards/targets/berkeleylab_marble.py +++ b/litex_boards/targets/berkeleylab_marble.py @@ -145,7 +145,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=berkeleylab_marble.Platform, description="LiteX SoC on BerkeleyLab Marble") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index 78d758e..36e942e 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -101,7 +101,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=camlink_4k.Platform, description="LiteX SoC on Cam Link 4K") parser.add_target_argument("--sys-clk-freq", default=81e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/colorlight_5a_75x.py b/litex_boards/targets/colorlight_5a_75x.py index 9d09c46..ce442fd 100755 --- a/litex_boards/targets/colorlight_5a_75x.py +++ b/litex_boards/targets/colorlight_5a_75x.py @@ -178,7 +178,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=colorlight_5a_75b.Platform, description="LiteX SoC on Colorlight 5A-75X") parser.add_target_argument("--board", default="5a-75b", help="Board type (5a-75b or 5a-75e).") parser.add_target_argument("--revision", default="7.0", type=str, help="Board revision (6.0, 6.1, 7.0 or 8.0).") diff --git a/litex_boards/targets/colorlight_i5.py b/litex_boards/targets/colorlight_i5.py index 8f1d181..7a05482 100755 --- a/litex_boards/targets/colorlight_i5.py +++ b/litex_boards/targets/colorlight_i5.py @@ -175,7 +175,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=colorlight_i5.Platform, description="LiteX SoC on Colorlight I5") parser.add_target_argument("--board", default="i5", help="Board type (i5).") parser.add_target_argument("--revision", default="7.0", type=str, help="Board revision (7.0).") diff --git a/litex_boards/targets/decklink_intensity_pro_4k.py b/litex_boards/targets/decklink_intensity_pro_4k.py index 7dd77ed..e0b40d6 100755 --- a/litex_boards/targets/decklink_intensity_pro_4k.py +++ b/litex_boards/targets/decklink_intensity_pro_4k.py @@ -61,7 +61,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=decklink_intensity_pro_4k.Platform, description="LiteX SoC Blackmagic Decklink Intensity Pro 4K") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/decklink_mini_4k.py b/litex_boards/targets/decklink_mini_4k.py index 8c33fb7..7d5aefa 100755 --- a/litex_boards/targets/decklink_mini_4k.py +++ b/litex_boards/targets/decklink_mini_4k.py @@ -148,7 +148,7 @@ class BaseSoC(SoCMini): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=decklink_mini_4k.Platform, description="LiteX SoC Blackmagic Decklink Mini 4K") parser.add_target_argument("--sys-clk-freq", default=148.5e6, help="System clock frequency.") pcieopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/decklink_quad_hdmi_recorder.py b/litex_boards/targets/decklink_quad_hdmi_recorder.py index d2ec97b..b90c574 100755 --- a/litex_boards/targets/decklink_quad_hdmi_recorder.py +++ b/litex_boards/targets/decklink_quad_hdmi_recorder.py @@ -106,7 +106,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=decklink_quad_hdmi_recorder.Platform, description="LiteX SoC on Blackmagic Decklink Quad HDMI Recorder") parser.add_target_argument("--sys-clk-freq", default=200e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index 1025422..d76a9e0 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -154,7 +154,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_arty.Platform, description="LiteX SoC on Arty A7") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).") diff --git a/litex_boards/targets/digilent_arty_s7.py b/litex_boards/targets/digilent_arty_s7.py index 0fd6ab9..fc30d01 100755 --- a/litex_boards/targets/digilent_arty_s7.py +++ b/litex_boards/targets/digilent_arty_s7.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_arty_s7.Platform, description="LiteX SoC on Arty S7") parser.add_target_argument("--variant", default="s7-50", help="Board variant (s7-50 or s7-25).") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index f05df57..24b6791 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -155,7 +155,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_arty_z7.Platform, description="LiteX SoC on Arty Z7") parser.add_target_argument("--variant", default="z7-20", help="Board variant (z7-20 or z7-10).") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") diff --git a/litex_boards/targets/digilent_atlys.py b/litex_boards/targets/digilent_atlys.py index 41d7bf9..1ff978d 100755 --- a/litex_boards/targets/digilent_atlys.py +++ b/litex_boards/targets/digilent_atlys.py @@ -205,7 +205,7 @@ NET "{eth_clocks_tx}" CLOCK_DEDICATED_ROUTE = FALSE; # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_atlys.Platform, description="LiteX SoC on Atlys") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") diff --git a/litex_boards/targets/digilent_basys3.py b/litex_boards/targets/digilent_basys3.py index 9c4e316..6c2316c 100755 --- a/litex_boards/targets/digilent_basys3.py +++ b/litex_boards/targets/digilent_basys3.py @@ -62,7 +62,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_basys3.Platform, description="LiteX SoC on Basys3") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") sdopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 4aa4766..483d666 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -135,7 +135,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_cmod_a7.Platform, description="LiteX SoC on CMOD A7") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).") diff --git a/litex_boards/targets/digilent_genesys2.py b/litex_boards/targets/digilent_genesys2.py index 540967d..325606b 100755 --- a/litex_boards/targets/digilent_genesys2.py +++ b/litex_boards/targets/digilent_genesys2.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_genesys2.Platform, description="LiteX SoC on Genesys2") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/digilent_nexys4.py b/litex_boards/targets/digilent_nexys4.py index b87ff7a..d4b1685 100755 --- a/litex_boards/targets/digilent_nexys4.py +++ b/litex_boards/targets/digilent_nexys4.py @@ -205,7 +205,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_nexys4.Platform, description="LiteX SoC on Nexys4") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/digilent_nexys4ddr.py b/litex_boards/targets/digilent_nexys4ddr.py index 7cbf5f7..ecd49d5 100755 --- a/litex_boards/targets/digilent_nexys4ddr.py +++ b/litex_boards/targets/digilent_nexys4ddr.py @@ -103,7 +103,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_nexys4ddr.Platform, description="LiteX SoC on Nexys4DDR") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/digilent_nexys_video.py b/litex_boards/targets/digilent_nexys_video.py index db0a314..fcee5f0 100755 --- a/litex_boards/targets/digilent_nexys_video.py +++ b/litex_boards/targets/digilent_nexys_video.py @@ -160,7 +160,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_nexys_video.Platform, description="LiteX SoC on Nexys Video") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/digilent_pynq_z1.py b/litex_boards/targets/digilent_pynq_z1.py index 55a8bc6..b4cda4b 100755 --- a/litex_boards/targets/digilent_pynq_z1.py +++ b/litex_boards/targets/digilent_pynq_z1.py @@ -98,7 +98,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_pynq_z1.Platform, description="LiteX SoC on PYNQ Z1") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).") diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 166c9be..fe8057b 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -145,7 +145,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_zedboard.Platform, description="LiteX SoC on Zedboard") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.set_defaults(cpu_type="zynq7000") diff --git a/litex_boards/targets/ebaz4205.py b/litex_boards/targets/ebaz4205.py index 99dad9e..425e499 100755 --- a/litex_boards/targets/ebaz4205.py +++ b/litex_boards/targets/ebaz4205.py @@ -65,7 +65,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=ebaz4205.Platform, description="LiteX SoC on EBAZ4205") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/efinix_t8f81_dev_kit.py b/litex_boards/targets/efinix_t8f81_dev_kit.py index 7f50a68..3b7daef 100755 --- a/litex_boards/targets/efinix_t8f81_dev_kit.py +++ b/litex_boards/targets/efinix_t8f81_dev_kit.py @@ -82,7 +82,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_t8f81_dev_kit.Platform, description="LiteX SoC on Efinix T8F81C Dev Kit") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.") diff --git a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py index 70f05d7..518bc55 100755 --- a/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py +++ b/litex_boards/targets/efinix_titanium_ti60_f225_dev_kit.py @@ -118,7 +118,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_titanium_ti60_f225_dev_kit.Platform, description="LiteX SoC on Efinix Titanium Ti60 F225 Dev Kit") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=200e6, help="System clock frequency.") diff --git a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py index 281543d..ac8f020 100755 --- a/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t120_bga576_dev_kit.py @@ -337,7 +337,7 @@ calc_result = design.auto_calc_pll_clock("dram_pll", {"CLKOUT0_FREQ": "400.0"}) # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_trion_t120_bga576_dev_kit.Platform, description="LiteX SoC on Efinix Trion T120 BGA576 Dev Kit") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") diff --git a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py index b257c38..94ea5bf 100755 --- a/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_bga256_dev_kit.py @@ -66,7 +66,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_trion_t20_bga256_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 BGA256 Dev Kit") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py index 9a1a990..aa7bf28 100755 --- a/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py +++ b/litex_boards/targets/efinix_trion_t20_mipi_dev_kit.py @@ -64,7 +64,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_trion_t20_mipi_dev_kit.Platform, description="LiteX SoC on Efinix Trion T20 MIPI Dev Kit") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed).") diff --git a/litex_boards/targets/efinix_xyloni_dev_kit.py b/litex_boards/targets/efinix_xyloni_dev_kit.py index d185920..d4fc230 100755 --- a/litex_boards/targets/efinix_xyloni_dev_kit.py +++ b/litex_boards/targets/efinix_xyloni_dev_kit.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=efinix_xyloni_dev_kit.Platform, description="LiteX SoC on Efinix Xyloni Dev Kit") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.") diff --git a/litex_boards/targets/ego1.py b/litex_boards/targets/ego1.py index 945270b..1a1b034 100755 --- a/litex_boards/targets/ego1.py +++ b/litex_boards/targets/ego1.py @@ -59,7 +59,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=ego1.Platform, description="LiteX SoC on EGO1") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal.") diff --git a/litex_boards/targets/enclustra_mercury_kx2.py b/litex_boards/targets/enclustra_mercury_kx2.py index e561b14..f4d6777 100755 --- a/litex_boards/targets/enclustra_mercury_kx2.py +++ b/litex_boards/targets/enclustra_mercury_kx2.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=enclustra_mercury_kx2.Platform, description="LiteX SoC on KX2") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/enclustra_mercury_xu5.py b/litex_boards/targets/enclustra_mercury_xu5.py index 5806246..e22bc82 100755 --- a/litex_boards/targets/enclustra_mercury_xu5.py +++ b/litex_boards/targets/enclustra_mercury_xu5.py @@ -83,7 +83,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=enclustra_mercury_xu5.Platform, description="LiteX SoC on Mercury XU5") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/fairwaves_xtrx.py b/litex_boards/targets/fairwaves_xtrx.py index 985e283..3c4cab9 100755 --- a/litex_boards/targets/fairwaves_xtrx.py +++ b/litex_boards/targets/fairwaves_xtrx.py @@ -103,7 +103,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=fairwaves_xtrx.Platform, description="LiteX SoC on Fairwaves XTRX") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") diff --git a/litex_boards/targets/fpc_iii.py b/litex_boards/targets/fpc_iii.py index 9ddc924..903840d 100755 --- a/litex_boards/targets/fpc_iii.py +++ b/litex_boards/targets/fpc_iii.py @@ -123,7 +123,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=fpc_iii.Platform, description="LiteX SoC on FPC-III") parser.add_target_argument("--sys-clk-freq", default=80e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/fpgawars_alhambra2.py b/litex_boards/targets/fpgawars_alhambra2.py index 70a8b88..0e5af7a 100755 --- a/litex_boards/targets/fpgawars_alhambra2.py +++ b/litex_boards/targets/fpgawars_alhambra2.py @@ -74,7 +74,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=fpgawars_alhambra2.Platform, description="LiteX SoC on Lattice iCE40UP5k EVN breakout board") parser.add_target_argument("--sys-clk-freq", default=12e6, help="System clock frequency.") diff --git a/litex_boards/targets/gsd_butterstick.py b/litex_boards/targets/gsd_butterstick.py index e3bad77..5483528 100755 --- a/litex_boards/targets/gsd_butterstick.py +++ b/litex_boards/targets/gsd_butterstick.py @@ -151,7 +151,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=gsd_butterstick.Platform, description="LiteX SoC on ButterStick") parser.add_target_argument("--programmer", default="jtag", help="Programming interface (jtag or dfu).") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index f4f6b00..82b2317 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -195,7 +195,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=gsd_orangecrab.Platform, description="LiteX SoC on OrangeCrab") parser.add_target_argument("--sys-clk-freq", default=48e6, help="System clock frequency.") parser.add_target_argument("--revision", default="0.2", help="Board Revision (0.1 or 0.2).") diff --git a/litex_boards/targets/hackaday_hadbadge.py b/litex_boards/targets/hackaday_hadbadge.py index 782118d..401e0db 100755 --- a/litex_boards/targets/hackaday_hadbadge.py +++ b/litex_boards/targets/hackaday_hadbadge.py @@ -74,7 +74,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=hackaday_hadbadge.Platform, description="LiteX SoC on Hackaday Badge") parser.add_target_argument("--sys-clk-freq", default=48e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/hpcstore_xc7k420t.py b/litex_boards/targets/hpcstore_xc7k420t.py index 6eef180..bd36e18 100755 --- a/litex_boards/targets/hpcstore_xc7k420t.py +++ b/litex_boards/targets/hpcstore_xc7k420t.py @@ -138,7 +138,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=hpcstore_xc7k420t.Platform, description="LiteX SoC on AliExpress HPC Store XC7K420T") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--io-voltage", default="3.3V", help="IO voltage chosen by Jumper J3. Can be: '3.3V' or '2.5V'") diff --git a/litex_boards/targets/icebreaker.py b/litex_boards/targets/icebreaker.py index d53bd17..aa39a34 100755 --- a/litex_boards/targets/icebreaker.py +++ b/litex_boards/targets/icebreaker.py @@ -132,7 +132,7 @@ def flash(build_dir, build_name, bios_flash_offset): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=icebreaker.Platform, description="LiteX SoC on iCEBreaker") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.") parser.add_target_argument("--sys-clk-freq", default=24e6, help="System clock frequency.") diff --git a/litex_boards/targets/icebreaker_bitsy.py b/litex_boards/targets/icebreaker_bitsy.py index 8df4627..60f3a18 100755 --- a/litex_boards/targets/icebreaker_bitsy.py +++ b/litex_boards/targets/icebreaker_bitsy.py @@ -144,7 +144,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=icebreaker_bitsy.Platform, description="LiteX SoC on iCEBreaker") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream and BIOS.") parser.add_target_argument("--sys-clk-freq", default=24e6, help="System clock frequency.") diff --git a/litex_boards/targets/jungle_electronics_fireant.py b/litex_boards/targets/jungle_electronics_fireant.py index 8b7b4b9..ce4bc93 100755 --- a/litex_boards/targets/jungle_electronics_fireant.py +++ b/litex_boards/targets/jungle_electronics_fireant.py @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=jungle_electronics_fireant.Platform, description="LiteX SoC on Jungle Electronics FireAnt") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq", default=33.333e6, help="System clock frequency.") diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index 77d8ef6..2fb1cee 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -157,7 +157,7 @@ def flash(build_dir, build_name, bios_flash_offset): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=kosagi_fomu_pvt.Platform, description="LiteX SoC on Fomu") parser.add_target_argument("--sys-clk-freq", default=12e6, help="System clock frequency.") parser.add_target_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.") diff --git a/litex_boards/targets/kosagi_netv2.py b/litex_boards/targets/kosagi_netv2.py index 47ba799..c0cc910 100755 --- a/litex_boards/targets/kosagi_netv2.py +++ b/litex_boards/targets/kosagi_netv2.py @@ -106,7 +106,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=kosagi_netv2.Platform, description="LiteX SoC on NeTV2") parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/krtkl_snickerdoodle.py b/litex_boards/targets/krtkl_snickerdoodle.py index a944117..21a2014 100755 --- a/litex_boards/targets/krtkl_snickerdoodle.py +++ b/litex_boards/targets/krtkl_snickerdoodle.py @@ -105,7 +105,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=krtkl_snickerdoodle.Platform, description="LiteX SoC on Snickerdoodle") parser.add_target_argument("--variant", default="z7-10", help="Board variant (z7-10 or z7-20).") parser.add_target_argument("--ext-clk-freq", default=10e6, type=float, help="External Clock Frequency.") diff --git a/litex_boards/targets/lambdaconcept_ecpix5.py b/litex_boards/targets/lambdaconcept_ecpix5.py index 01d9e9d..d48819b 100755 --- a/litex_boards/targets/lambdaconcept_ecpix5.py +++ b/litex_boards/targets/lambdaconcept_ecpix5.py @@ -220,7 +220,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lambdaconcept_ecpix5.Platform, description="LiteX SoC on ECPIX-5") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.") parser.add_target_argument("--device", default="85F", help="ECP5 device (45F or 85F).") diff --git a/litex_boards/targets/lattice_crosslink_nx_evn.py b/litex_boards/targets/lattice_crosslink_nx_evn.py index 0c35c5f..4521bfe 100755 --- a/litex_boards/targets/lattice_crosslink_nx_evn.py +++ b/litex_boards/targets/lattice_crosslink_nx_evn.py @@ -91,7 +91,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_crosslink_nx_evn.Platform, description="LiteX SoC on Crosslink-NX Eval Board") parser.add_target_argument("--device", default="LIFCL-40-9BG400C", help="FPGA device (LIFCL-40-9BG400C, LIFCL-40-8BG400CES, or LIFCL-40-8BG400CES2).") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") diff --git a/litex_boards/targets/lattice_crosslink_nx_vip.py b/litex_boards/targets/lattice_crosslink_nx_vip.py index 59d314d..fd29c26 100755 --- a/litex_boards/targets/lattice_crosslink_nx_vip.py +++ b/litex_boards/targets/lattice_crosslink_nx_vip.py @@ -99,7 +99,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_crosslink_nx_vip.Platform, description="LiteX SoC on Crosslink-NX VIP Board") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") parser.add_target_argument("--with-hyperram", default="none", help="Enable use of HyperRAM chip (none, 0 or 1).") diff --git a/litex_boards/targets/lattice_ecp5_evn.py b/litex_boards/targets/lattice_ecp5_evn.py index 3238b0f..4a23d02 100755 --- a/litex_boards/targets/lattice_ecp5_evn.py +++ b/litex_boards/targets/lattice_ecp5_evn.py @@ -63,7 +63,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_ecp5_evn.Platform, description="LiteX SoC on ECP5 Evaluation Board") parser.add_target_argument("--sys-clk-freq", default=60e6, help="System clock frequency.") parser.add_target_argument("--x5-clk-freq", type=int, help="Use X5 oscillator as system clock at the specified frequency.") diff --git a/litex_boards/targets/lattice_ecp5_vip.py b/litex_boards/targets/lattice_ecp5_vip.py index 577df15..f895c60 100755 --- a/litex_boards/targets/lattice_ecp5_vip.py +++ b/litex_boards/targets/lattice_ecp5_vip.py @@ -186,7 +186,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_ecp5_vip.Platform, description="LiteX SoC on ECP5 Evaluation Board") parser.add_target_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)") args = parser.parse_args() diff --git a/litex_boards/targets/lattice_ice40up5k_evn.py b/litex_boards/targets/lattice_ice40up5k_evn.py index a67318a..a3c2dad 100755 --- a/litex_boards/targets/lattice_ice40up5k_evn.py +++ b/litex_boards/targets/lattice_ice40up5k_evn.py @@ -129,7 +129,7 @@ def flash(bios_flash_offset, target="lattice_ice40up5k_evn"): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_ice40up5k_evn.Platform, description="LiteX SoC on Lattice iCE40UP5k EVN breakout board") parser.add_target_argument("--sys-clk-freq", default=12e6, help="System clock frequency.") parser.add_target_argument("--bios-flash-offset", default="0x20000", help="BIOS offset in SPI Flash.") diff --git a/litex_boards/targets/lattice_versa_ecp5.py b/litex_boards/targets/lattice_versa_ecp5.py index f4a3424..647d416 100755 --- a/litex_boards/targets/lattice_versa_ecp5.py +++ b/litex_boards/targets/lattice_versa_ecp5.py @@ -119,7 +119,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=lattice_versa_ecp5.Platform, description="LiteX SoC on Versa ECP5") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") parser.add_target_argument("--device", default="LFE5UM5G", help="FPGA device (LFE5UM5G or LFE5UM).") diff --git a/litex_boards/targets/limesdr_mini_v2.py b/litex_boards/targets/limesdr_mini_v2.py index d6132b2..e1fd886 100755 --- a/litex_boards/targets/limesdr_mini_v2.py +++ b/litex_boards/targets/limesdr_mini_v2.py @@ -136,7 +136,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=limesdr_mini_v2.Platform, description="LiteX SoC on LimeSDR-Mini-V2") parser.add_target_argument("--sys-clk-freq", default=80e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/linsn_rv901t.py b/litex_boards/targets/linsn_rv901t.py index e55a0ee..dbdaae4 100755 --- a/litex_boards/targets/linsn_rv901t.py +++ b/litex_boards/targets/linsn_rv901t.py @@ -89,7 +89,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=linsn_rv901t.Platform, description="LiteX SoC on Linsn RV901T") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/litex_acorn_baseboard.py b/litex_boards/targets/litex_acorn_baseboard.py index 13d2353..f994506 100755 --- a/litex_boards/targets/litex_acorn_baseboard.py +++ b/litex_boards/targets/litex_acorn_baseboard.py @@ -119,7 +119,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=litex_acorn_baseboard.Platform, description="LiteX SoC on LiteX Acorn Baseboard") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream to SPI Flash.") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 494fe97..a066048 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -142,7 +142,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=logicbone.Platform, description="LiteX SoC on Logicbone") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") parser.add_target_argument("--device", default="45F", help="FPGA device (45F or 85F).") diff --git a/litex_boards/targets/machdyne_schoko.py b/litex_boards/targets/machdyne_schoko.py index 1906328..bba2956 100755 --- a/litex_boards/targets/machdyne_schoko.py +++ b/litex_boards/targets/machdyne_schoko.py @@ -171,7 +171,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=machdyne_schoko.Platform, description="LiteX SoC on Schoko") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream to MMOD.") parser.add_target_argument("--sys-clk-freq", default=40e6, help="System clock frequency.") diff --git a/litex_boards/targets/micronova_mercury2.py b/litex_boards/targets/micronova_mercury2.py index 72bbb8b..cf4cde1 100755 --- a/litex_boards/targets/micronova_mercury2.py +++ b/litex_boards/targets/micronova_mercury2.py @@ -131,7 +131,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=micronova_mercury2.Platform, description="LiteX SoC on MicroNova Mercury2") parser.add_target_argument("--variant", default="a7-35", help="Board variant (a7-35 or a7-100).") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") diff --git a/litex_boards/targets/mist.py b/litex_boards/targets/mist.py index 379cee6..2064234 100755 --- a/litex_boards/targets/mist.py +++ b/litex_boards/targets/mist.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=mist.Platform, description="LiteX SoC on MIST") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") diff --git a/litex_boards/targets/mnt_rkx7.py b/litex_boards/targets/mnt_rkx7.py index 9149ade..acf5de0 100755 --- a/litex_boards/targets/mnt_rkx7.py +++ b/litex_boards/targets/mnt_rkx7.py @@ -193,7 +193,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=mnt_rkx7.Platform, description="LiteX SoC on MNT-RKX7") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-spi-flash", action="store_true", default=True, help="Enable SPI Flash (MMAPed).") diff --git a/litex_boards/targets/muselab_icesugar.py b/litex_boards/targets/muselab_icesugar.py index 1c1b753..749bdca 100755 --- a/litex_boards/targets/muselab_icesugar.py +++ b/litex_boards/targets/muselab_icesugar.py @@ -107,7 +107,7 @@ def flash(bios_flash_offset): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=muselab_icesugar.Platform, description="LiteX SoC on iCEBreaker") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq", default=24e6, help="System clock frequency.") diff --git a/litex_boards/targets/muselab_icesugar_pro.py b/litex_boards/targets/muselab_icesugar_pro.py index c670462..28dda92 100755 --- a/litex_boards/targets/muselab_icesugar_pro.py +++ b/litex_boards/targets/muselab_icesugar_pro.py @@ -142,7 +142,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=muselab_icesugar_pro.Platform, description="LiteX SoC on Colorlight i5") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") sdopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/myminieye_runber.py b/litex_boards/targets/myminieye_runber.py index c2b99db..186165c 100755 --- a/litex_boards/targets/myminieye_runber.py +++ b/litex_boards/targets/myminieye_runber.py @@ -56,7 +56,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=myminieye_runber.Platform, description="LiteX SoC on Runber") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq",default=12e6, help="System clock frequency.") diff --git a/litex_boards/targets/newae_cw305.py b/litex_boards/targets/newae_cw305.py index 76dd48c..bf96207 100755 --- a/litex_boards/targets/newae_cw305.py +++ b/litex_boards/targets/newae_cw305.py @@ -81,7 +81,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=newae_cw305.Platform, description="LiteX SoC on NewAE-CW305") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/numato_aller.py b/litex_boards/targets/numato_aller.py index 371f559..8b47b13 100755 --- a/litex_boards/targets/numato_aller.py +++ b/litex_boards/targets/numato_aller.py @@ -96,7 +96,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=numato_aller.Platform, description="LiteX SoC on Aller") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/numato_mimas_a7.py b/litex_boards/targets/numato_mimas_a7.py index 631b51e..2bd4cd1 100755 --- a/litex_boards/targets/numato_mimas_a7.py +++ b/litex_boards/targets/numato_mimas_a7.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=numato_mimas_a7.Platform, description="LiteX SoC on Mimas A7") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/numato_nereid.py b/litex_boards/targets/numato_nereid.py index d0e0ef5..221b803 100755 --- a/litex_boards/targets/numato_nereid.py +++ b/litex_boards/targets/numato_nereid.py @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=numato_nereid.Platform, description="LiteX SoC on Nereid") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/numato_tagus.py b/litex_boards/targets/numato_tagus.py index b2b6d82..ee3d580 100755 --- a/litex_boards/targets/numato_tagus.py +++ b/litex_boards/targets/numato_tagus.py @@ -96,7 +96,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=numato_tagus.Platform, description="LiteX SoC on Tagus") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/pano_logic_g2.py b/litex_boards/targets/pano_logic_g2.py index d1b92d8..24cd688 100755 --- a/litex_boards/targets/pano_logic_g2.py +++ b/litex_boards/targets/pano_logic_g2.py @@ -79,7 +79,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=pano_logic_g2.Platform, description="LiteX SoC on Pano Logic G2") parser.add_target_argument("--revision", default="c", help="Board revision (b or c).") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py index f2e71bc..0aee41b 100755 --- a/litex_boards/targets/qmtech_10cl006.py +++ b/litex_boards/targets/qmtech_10cl006.py @@ -103,7 +103,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_10cl006.Platform, description="LiteX SoC on QMTECH 10CL006") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:2", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/qmtech_5cefa2.py b/litex_boards/targets/qmtech_5cefa2.py index 9f824ee..b6aa9fe 100755 --- a/litex_boards/targets/qmtech_5cefa2.py +++ b/litex_boards/targets/qmtech_5cefa2.py @@ -131,7 +131,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_5cefa2.Platform, description="LiteX SoC on QMTECH 5CEFA2") parser.add_target_argument("--sys-clk-freq", default=105e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py index 6fd2bd2..89b4f82 100755 --- a/litex_boards/targets/qmtech_ep4ce15_starter_kit.py +++ b/litex_boards/targets/qmtech_ep4ce15_starter_kit.py @@ -103,7 +103,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_ep4ce15_starter_kit.Platform, description="LiteX SoC on QMTECH EP4CE15") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/qmtech_ep4cex5.py b/litex_boards/targets/qmtech_ep4cex5.py index 98249dc..7034f5e 100755 --- a/litex_boards/targets/qmtech_ep4cex5.py +++ b/litex_boards/targets/qmtech_ep4cex5.py @@ -129,7 +129,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_ep4cex5.Platform, description="LiteX SoC on QMTECH EP4CE15") parser.add_target_argument("--variant", default="ep4ce15", help="Board variant (ep4ce15 or ep4ce55).") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") diff --git a/litex_boards/targets/qmtech_ep4cgx150.py b/litex_boards/targets/qmtech_ep4cgx150.py index c96eda4..c422aac 100755 --- a/litex_boards/targets/qmtech_ep4cgx150.py +++ b/litex_boards/targets/qmtech_ep4cgx150.py @@ -128,7 +128,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_ep4cgx150.Platform, description="LiteX SoC on QMTECH EP4CE15") parser.add_target_argument("--sys-clk-freq", default=80e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/qmtech_wukong.py b/litex_boards/targets/qmtech_wukong.py index a3b6e02..78819e6 100755 --- a/litex_boards/targets/qmtech_wukong.py +++ b/litex_boards/targets/qmtech_wukong.py @@ -127,7 +127,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_wukong.Platform, description="LiteX SoC on QMTECH Wukong Board") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--board-version", default=1, help="Board version (1 or 2).") diff --git a/litex_boards/targets/qmtech_xc7a35t.py b/litex_boards/targets/qmtech_xc7a35t.py index d8805ed..d018afb 100755 --- a/litex_boards/targets/qmtech_xc7a35t.py +++ b/litex_boards/targets/qmtech_xc7a35t.py @@ -140,7 +140,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qmtech_xc7a35t.Platform, description="LiteX SoC on QMTech XC7A35T") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-daughterboard", action="store_true", help="Board plugged into the QMTech daughterboard.") diff --git a/litex_boards/targets/quicklogic_quickfeather.py b/litex_boards/targets/quicklogic_quickfeather.py index 511a45f..9b4f0ed 100755 --- a/litex_boards/targets/quicklogic_quickfeather.py +++ b/litex_boards/targets/quicklogic_quickfeather.py @@ -89,7 +89,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=quicklogic_quickfeather.Platform, description="LiteX SoC on QuickLogic QuickFeather") parser.set_defaults(cpu_type="eos_s3") args = parser.parse_args() diff --git a/litex_boards/targets/qwertyembedded_beaglewire.py b/litex_boards/targets/qwertyembedded_beaglewire.py index 7a2050b..2aa1e6a 100755 --- a/litex_boards/targets/qwertyembedded_beaglewire.py +++ b/litex_boards/targets/qwertyembedded_beaglewire.py @@ -108,7 +108,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=qwertyembedded_beaglewire.Platform, description="LiteX SoC on Beaglewire") parser.add_target_argument("--bios-flash-offset", default="0x60000", help="BIOS offset in SPI Flash.") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") diff --git a/litex_boards/targets/radiona_ulx3s.py b/litex_boards/targets/radiona_ulx3s.py index 26a614b..89bf38a 100755 --- a/litex_boards/targets/radiona_ulx3s.py +++ b/litex_boards/targets/radiona_ulx3s.py @@ -142,7 +142,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=radiona_ulx3s.Platform, description="LiteX SoC on ULX3S") parser.add_target_argument("--device", default="LFE5U-45F", help="FPGA device (LFE5U-12F, LFE5U-25F, LFE5U-45F or LFE5U-85F).") parser.add_target_argument("--revision", default="2.0", help="Board revision (2.0 or 1.7).") diff --git a/litex_boards/targets/rcs_arctic_tern_bmc_card.py b/litex_boards/targets/rcs_arctic_tern_bmc_card.py index ee56884..f73c266 100755 --- a/litex_boards/targets/rcs_arctic_tern_bmc_card.py +++ b/litex_boards/targets/rcs_arctic_tern_bmc_card.py @@ -154,7 +154,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=rcs_arctic_tern_bmc_card.Platform, description="LiteX SoC on Arctic Tern (BMC card carrier)") parser.add_target_argument("--sys-clk-freq", default=60e6, help="System clock frequency (default: 60MHz)") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/redpitaya.py b/litex_boards/targets/redpitaya.py index cbcf577..9d9ac16 100755 --- a/litex_boards/targets/redpitaya.py +++ b/litex_boards/targets/redpitaya.py @@ -94,7 +94,7 @@ class BaseSoC(SoCCore): def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=redpitaya.Platform, description="LiteX SoC on Zedboard") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--board", default="redpitaya14", help="Board type (redpitaya14 or redpitaya16).") diff --git a/litex_boards/targets/rz_easyfpga.py b/litex_boards/targets/rz_easyfpga.py index 725eb25..1d5487f 100755 --- a/litex_boards/targets/rz_easyfpga.py +++ b/litex_boards/targets/rz_easyfpga.py @@ -90,7 +90,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=rz_easyfpga.Platform, description="LiteX SoC on RZ-EasyFPGA") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/saanlima_pipistrello.py b/litex_boards/targets/saanlima_pipistrello.py index f5632a1..98aea7d 100755 --- a/litex_boards/targets/saanlima_pipistrello.py +++ b/litex_boards/targets/saanlima_pipistrello.py @@ -189,7 +189,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=saanlima_pipistrello.Platform, description="LiteX SoC on Pipistrello") args = parser.parse_args() diff --git a/litex_boards/targets/scarabhardware_minispartan6.py b/litex_boards/targets/scarabhardware_minispartan6.py index d29b896..3deccf2 100755 --- a/litex_boards/targets/scarabhardware_minispartan6.py +++ b/litex_boards/targets/scarabhardware_minispartan6.py @@ -103,7 +103,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=scarabhardware_minispartan6.Platform, description="LiteX SoC on MiniSpartan6") parser.add_target_argument("--sys-clk-freq", default=80e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py index 3a6907d..0b428e4 100755 --- a/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py +++ b/litex_boards/targets/seeedstudio_spartan_edge_accelerator.py @@ -105,7 +105,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=seeedstudio_spartan_edge_accelerator.Platform, description="LiteX SoC on Spartan Edge Accelerator") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-jtagbone", action="store_true", help="Enable Jtagbone support.") diff --git a/litex_boards/targets/siglent_sds1104xe.py b/litex_boards/targets/siglent_sds1104xe.py index a609fd2..e34b7f6 100755 --- a/litex_boards/targets/siglent_sds1104xe.py +++ b/litex_boards/targets/siglent_sds1104xe.py @@ -161,7 +161,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=siglent_sds1104xe.Platform, description="LiteX SoC on SDS1104X-E") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index c6cd48e..08eaef6 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -44,7 +44,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(description="Generic LiteX SoC") parser.add_target_argument("platform", help="Module name of the platform to build for.") args = parser.parse_args() diff --git a/litex_boards/targets/sipeed_tang_nano.py b/litex_boards/targets/sipeed_tang_nano.py index 605a360..5d9f81e 100755 --- a/litex_boards/targets/sipeed_tang_nano.py +++ b/litex_boards/targets/sipeed_tang_nano.py @@ -84,7 +84,7 @@ class BaseSoC(SoCMini): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sipeed_tang_nano.Platform, description="LiteX SoC on Tang Nano") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq",default=48e6, help="System clock frequency.") diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py index 22c56da..26eec65 100755 --- a/litex_boards/targets/sipeed_tang_nano_4k.py +++ b/litex_boards/targets/sipeed_tang_nano_4k.py @@ -137,7 +137,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sipeed_tang_nano_4k.Platform, description="LiteX SoC on Tang Nano 4K") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq",default=27e6, help="System clock frequency.") diff --git a/litex_boards/targets/sipeed_tang_nano_9k.py b/litex_boards/targets/sipeed_tang_nano_9k.py index c0a8123..93f7ba0 100755 --- a/litex_boards/targets/sipeed_tang_nano_9k.py +++ b/litex_boards/targets/sipeed_tang_nano_9k.py @@ -131,7 +131,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sipeed_tang_nano_9k.Platform, description="LiteX SoC on Tang Nano 9K") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq", default=27e6, help="System clock frequency.") diff --git a/litex_boards/targets/sipeed_tang_primer.py b/litex_boards/targets/sipeed_tang_primer.py index 416b556..5059304 100755 --- a/litex_boards/targets/sipeed_tang_primer.py +++ b/litex_boards/targets/sipeed_tang_primer.py @@ -59,7 +59,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sipeed_tang_primer.Platform, description="LiteX SoC on Tang Primer") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") parser.add_target_argument("--sys-clk-freq",default=24e6, help="System clock frequency.") diff --git a/litex_boards/targets/sipeed_tang_primer_20k.py b/litex_boards/targets/sipeed_tang_primer_20k.py index 9083c79..62e7eec 100755 --- a/litex_boards/targets/sipeed_tang_primer_20k.py +++ b/litex_boards/targets/sipeed_tang_primer_20k.py @@ -210,7 +210,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sipeed_tang_primer_20k.Platform, description="LiteX SoC on Tang Primer 20K") parser.add_target_argument("--dock", default="standard", help="Dock version (standard (default) or lite.") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream.") diff --git a/litex_boards/targets/sitlinv_a_e115fb.py b/litex_boards/targets/sitlinv_a_e115fb.py index 5076705..9fce892 100755 --- a/litex_boards/targets/sitlinv_a_e115fb.py +++ b/litex_boards/targets/sitlinv_a_e115fb.py @@ -57,7 +57,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sitlinv_a_e115fb.Platform, description="LiteX SoC on A-E115FB") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/sitlinv_stlv7325.py b/litex_boards/targets/sitlinv_stlv7325.py index ad8e350..cc89a27 100755 --- a/litex_boards/targets/sitlinv_stlv7325.py +++ b/litex_boards/targets/sitlinv_stlv7325.py @@ -140,7 +140,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sitlinv_stlv7325.Platform, description="LiteX SoC on AliExpress STLV7325") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/sqrl_acorn.py b/litex_boards/targets/sqrl_acorn.py index 6b494dc..7cbc06b 100755 --- a/litex_boards/targets/sqrl_acorn.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -172,7 +172,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sqrl_acorn.Platform, description="LiteX SoC on Acorn CLE-101/215(+)") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--variant", default="cle-215+", help="Board variant (cle-215+, cle-215 or cle-101).") diff --git a/litex_boards/targets/sqrl_fk33.py b/litex_boards/targets/sqrl_fk33.py index 66385bd..b276e4d 100755 --- a/litex_boards/targets/sqrl_fk33.py +++ b/litex_boards/targets/sqrl_fk33.py @@ -136,7 +136,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sqrl_fk33.Platform, description="LiteX SoC on FK33") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/sqrl_xcu1525.py b/litex_boards/targets/sqrl_xcu1525.py index 59d53b1..1e745df 100755 --- a/litex_boards/targets/sqrl_xcu1525.py +++ b/litex_boards/targets/sqrl_xcu1525.py @@ -133,7 +133,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=sqrl_xcu1525.Platform, description="LiteX SoC on XCU1525") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).") diff --git a/litex_boards/targets/terasic_de0nano.py b/litex_boards/targets/terasic_de0nano.py index bcedd20..253dd5b 100755 --- a/litex_boards/targets/terasic_de0nano.py +++ b/litex_boards/targets/terasic_de0nano.py @@ -90,7 +90,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_de0nano.Platform, description="LiteX SoC on DE0-Nano") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).") diff --git a/litex_boards/targets/terasic_de10lite.py b/litex_boards/targets/terasic_de10lite.py index 0a63702..9f837c0 100755 --- a/litex_boards/targets/terasic_de10lite.py +++ b/litex_boards/targets/terasic_de10lite.py @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_de10lite.Platform, description="LiteX SoC on DE10-Lite") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") diff --git a/litex_boards/targets/terasic_de10nano.py b/litex_boards/targets/terasic_de10nano.py index bea034b..9c32d8d 100755 --- a/litex_boards/targets/terasic_de10nano.py +++ b/litex_boards/targets/terasic_de10nano.py @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_de10nano.Platform, description="LiteX SoC on DE10-Nano") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--with-mister-sdram", action="store_true", help="Enable SDRAM with MiSTer expansion board.") diff --git a/litex_boards/targets/terasic_de1soc.py b/litex_boards/targets/terasic_de1soc.py index e79331b..7076e1b 100755 --- a/litex_boards/targets/terasic_de1soc.py +++ b/litex_boards/targets/terasic_de1soc.py @@ -76,7 +76,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_de1soc.Platform, description="LiteX SoC on DE1-SoC") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/terasic_de2_115.py b/litex_boards/targets/terasic_de2_115.py index 06bed18..2557544 100755 --- a/litex_boards/targets/terasic_de2_115.py +++ b/litex_boards/targets/terasic_de2_115.py @@ -69,7 +69,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_de2_115.Platform, description="LiteX SoC on DE2-115") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py index 10b752c..894f639 100755 --- a/litex_boards/targets/terasic_deca.py +++ b/litex_boards/targets/terasic_deca.py @@ -116,7 +116,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_deca.Platform, description="LiteX SoC on DECA") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/terasic_sockit.py b/litex_boards/targets/terasic_sockit.py index 65edb1b..df2f87d 100755 --- a/litex_boards/targets/terasic_sockit.py +++ b/litex_boards/targets/terasic_sockit.py @@ -109,7 +109,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=terasic_sockit.Platform, description="LiteX SoC on the Terasic SoCKit") parser.add_target_argument("--single-rate-sdram", action="store_true", help="Clock SDRAM with 1x the sytem clock (instead of 2x).") parser.add_target_argument("--mister-sdram-xs-v22", action="store_true", help="Use optional MiSTer SDRAM module XS v2.2 on J2 on GPIO daughter card.") diff --git a/litex_boards/targets/tinyfpga_bx.py b/litex_boards/targets/tinyfpga_bx.py index cba2f9a..a051238 100755 --- a/litex_boards/targets/tinyfpga_bx.py +++ b/litex_boards/targets/tinyfpga_bx.py @@ -58,7 +58,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=tinyfpga_bx.Platform, description="LiteX SoC on TinyFPGA BX") parser.add_target_argument("--bios-flash-offset", default="0x50000", help="BIOS offset in SPI Flash.") parser.add_target_argument("--sys-clk-freq", default=16e6, help="System clock frequency.") diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index c429d28..bf3a94d 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -176,7 +176,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trellisboard.Platform, description="LiteX SoC on Trellis Board") parser.add_target_argument("--sys-clk-freq", default=75e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/trenz_c10lprefkit.py b/litex_boards/targets/trenz_c10lprefkit.py index 5bba71b..4b1474e 100755 --- a/litex_boards/targets/trenz_c10lprefkit.py +++ b/litex_boards/targets/trenz_c10lprefkit.py @@ -101,7 +101,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trenz_c10lprefkit.Platform, description="LiteX SoC on C10 LP RefKit") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/trenz_cyc1000.py b/litex_boards/targets/trenz_cyc1000.py index f31bb24..aba04c3 100755 --- a/litex_boards/targets/trenz_cyc1000.py +++ b/litex_boards/targets/trenz_cyc1000.py @@ -73,7 +73,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trenz_cyc1000.Platform, description="LiteX SoC on CYC1000") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/trenz_max1000.py b/litex_boards/targets/trenz_max1000.py index 3db1941..0b6d43a 100755 --- a/litex_boards/targets/trenz_max1000.py +++ b/litex_boards/targets/trenz_max1000.py @@ -75,7 +75,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trenz_max1000.Platform, description="LiteX SoC on MAX1000") parser.add_target_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/trenz_te0725.py b/litex_boards/targets/trenz_te0725.py index 1a6e3c9..7c785d6 100755 --- a/litex_boards/targets/trenz_te0725.py +++ b/litex_boards/targets/trenz_te0725.py @@ -59,7 +59,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trenz_te0725.Platform, description="LiteX SoC on Trenz TE0725") parser.add_target_argument("--flash", action="store_true", help="Flash bitstream.") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") diff --git a/litex_boards/targets/trenz_tec0117.py b/litex_boards/targets/trenz_tec0117.py index dfa663c..0b3a7bb 100755 --- a/litex_boards/targets/trenz_tec0117.py +++ b/litex_boards/targets/trenz_tec0117.py @@ -150,7 +150,7 @@ def flash(bios_flash_offset): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=trenz_tec0117.Platform, description="LiteX SoC on TEC0117") parser.add_target_argument("--bios-flash-offset", default="0x0000", help="BIOS offset in SPI Flash.") parser.add_target_argument("--flash", action="store_true", help="Flash Bitstream and BIOS.") diff --git a/litex_boards/targets/tul_pynq_z2.py b/litex_boards/targets/tul_pynq_z2.py index 8e86534..7b2d3e2 100755 --- a/litex_boards/targets/tul_pynq_z2.py +++ b/litex_boards/targets/tul_pynq_z2.py @@ -67,7 +67,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=tul_pynq_z2.Platform, description="LiteX SoC on Pynq Z2") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/xilinx_ac701.py b/litex_boards/targets/xilinx_ac701.py index 32d0540..f24b71d 100755 --- a/litex_boards/targets/xilinx_ac701.py +++ b/litex_boards/targets/xilinx_ac701.py @@ -138,7 +138,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_ac701.Platform, description="LiteX SoC on AC701") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/xilinx_alveo_u280.py b/litex_boards/targets/xilinx_alveo_u280.py index b4f00e5..a44b2dd 100755 --- a/litex_boards/targets/xilinx_alveo_u280.py +++ b/litex_boards/targets/xilinx_alveo_u280.py @@ -155,7 +155,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_alveo_u280.Platform, description="LiteX SoC on Alveo U280") parser.add_target_argument("--sys-clk-freq", default=150e6, help="System clock frequency.") # HBM2 with 250MHz, DDR4 with 150MHz (1:4) parser.add_target_argument("--ddram-channel", default="0", help="DDRAM channel (0, 1, 2 or 3).") # also selects clk 0 or 1 diff --git a/litex_boards/targets/xilinx_kc705.py b/litex_boards/targets/xilinx_kc705.py index 0350c33..7ae2d3a 100755 --- a/litex_boards/targets/xilinx_kc705.py +++ b/litex_boards/targets/xilinx_kc705.py @@ -139,7 +139,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_kc705.Platform, description="LiteX SoC on KC705") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") diff --git a/litex_boards/targets/xilinx_kcu105.py b/litex_boards/targets/xilinx_kcu105.py index d239aed..611b495 100755 --- a/litex_boards/targets/xilinx_kcu105.py +++ b/litex_boards/targets/xilinx_kcu105.py @@ -148,7 +148,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_kcu105.Platform, description="LiteX SoC on KCU105") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") ethopts = parser.target_group.add_mutually_exclusive_group() diff --git a/litex_boards/targets/xilinx_kv260.py b/litex_boards/targets/xilinx_kv260.py index eaefae5..ca206d9 100755 --- a/litex_boards/targets/xilinx_kv260.py +++ b/litex_boards/targets/xilinx_kv260.py @@ -206,7 +206,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_kv260.Platform, description="LiteX SoC on KV260") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.set_defaults(cpu_type="zynqmp") diff --git a/litex_boards/targets/xilinx_vc707.py b/litex_boards/targets/xilinx_vc707.py index 0b2bdec..5dd64eb 100755 --- a/litex_boards/targets/xilinx_vc707.py +++ b/litex_boards/targets/xilinx_vc707.py @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_vc707.Platform, description="LiteX SoC on VC707") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support.") diff --git a/litex_boards/targets/xilinx_vcu118.py b/litex_boards/targets/xilinx_vcu118.py index efb956d..37f08b6 100755 --- a/litex_boards/targets/xilinx_vcu118.py +++ b/litex_boards/targets/xilinx_vcu118.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_vcu118.Platform, description="LiteX SoC on VCU118") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/xilinx_zcu102.py b/litex_boards/targets/xilinx_zcu102.py index 036d36c..b5fef72 100755 --- a/litex_boards/targets/xilinx_zcu102.py +++ b/litex_boards/targets/xilinx_zcu102.py @@ -41,7 +41,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_zcu102.Platform, description="LiteX SoC on ZCU102") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock generator.") args = parser.parse_args() diff --git a/litex_boards/targets/xilinx_zcu104.py b/litex_boards/targets/xilinx_zcu104.py index 49f9993..96af966 100755 --- a/litex_boards/targets/xilinx_zcu104.py +++ b/litex_boards/targets/xilinx_zcu104.py @@ -86,7 +86,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_zcu104.Platform, description="LiteX SoC on ZCU104") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/xilinx_zcu106.py b/litex_boards/targets/xilinx_zcu106.py index 49d9024..346dac9 100755 --- a/litex_boards/targets/xilinx_zcu106.py +++ b/litex_boards/targets/xilinx_zcu106.py @@ -98,7 +98,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_zcu106.Platform, description="LiteX SoC on ZCU106") parser.add_target_argument("--sys-clk-freq", default=125e6, help="System clock frequency.") parser.add_target_argument("--with-pcie", action="store_true", help="Enable PCIe support") diff --git a/litex_boards/targets/xilinx_zcu216.py b/litex_boards/targets/xilinx_zcu216.py index b2cce5b..5c2d86d 100755 --- a/litex_boards/targets/xilinx_zcu216.py +++ b/litex_boards/targets/xilinx_zcu216.py @@ -193,7 +193,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=xilinx_zcu216.Platform, description="LiteX SoC on ZCU216") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") parser.set_defaults(cpu_type="zynqmp") diff --git a/litex_boards/targets/xilinx_zybo_z7.py b/litex_boards/targets/xilinx_zybo_z7.py index aebefa5..771ec49 100755 --- a/litex_boards/targets/xilinx_zybo_z7.py +++ b/litex_boards/targets/xilinx_zybo_z7.py @@ -79,7 +79,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=digilent_zybo_z7.Platform, description="LiteX SoC on Zybo Z7") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.") args = parser.parse_args() diff --git a/litex_boards/targets/ztex213.py b/litex_boards/targets/ztex213.py index 03cd399..304874a 100755 --- a/litex_boards/targets/ztex213.py +++ b/litex_boards/targets/ztex213.py @@ -91,7 +91,7 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - from litex.build.argument_parser import LiteXArgumentParser + from litex.build.parser import LiteXArgumentParser parser = LiteXArgumentParser(platform=ztex213.Platform, description="LiteX SoC on Ztex 2.13") parser.add_target_argument("--expansion", default="debug", help="Expansion board (debug or sbus).") parser.add_target_argument("--sys-clk-freq", default=100e6, help="System clock frequency.")