From 396b0383c8fff0c41f12a40a1948b1ef5e365c24 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Thu, 19 Mar 2020 09:53:09 -0400 Subject: [PATCH 1/3] platforms/trellisboard: fix "sdcard" pads, add "spisdcard" pads Add support for SPI-mode SDCard interface. Also, add pull-up and slew constraints to the standard sdcard interface. Signed-off-by: Gabriel Somlo --- litex_boards/platforms/trellisboard.py | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/trellisboard.py b/litex_boards/platforms/trellisboard.py index 99ce16d..509dbfe 100644 --- a/litex_boards/platforms/trellisboard.py +++ b/litex_boards/platforms/trellisboard.py @@ -140,11 +140,19 @@ _io = [ Subsignal("uart_cts_n", Pins("P7"), IOStandard("LVCMOS33")) ), + ("spisdcard", 0, + Subsignal("clk", Pins("AK3")), + Subsignal("mosi", Pins("AH3"), Misc("PULLMODE=UP")), + Subsignal("cs_n", Pins("AK1"), Misc("PULLMODE=UP")), + Subsignal("miso", Pins("AG1"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") + ), + ("sdcard", 0, - Subsignal("data", Pins("AG1 AJ1 AH1 AK1")), Subsignal("clk", Pins("AK3")), - Subsignal("cmd", Pins("AH3")), - IOStandard("LVCMOS33") + Subsignal("cmd", Pins("AH3"), Misc("PULLMODE=UP")), + Subsignal("data", Pins("AG1 AJ1 AH1 AK1"), Misc("PULLMODE=UP")), + IOStandard("LVCMOS33"), Misc("SLEW=FAST") ), ("spiflash4x", 0, From 69a78c8c66483d435bc16f3e3a40aa1b433a9d12 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Wed, 18 Mar 2020 15:06:38 -0400 Subject: [PATCH 2/3] targets/trellisboard: switch to SoCCore, use add_ethernet() method Signed-off-by: Gabriel Somlo --- litex_boards/targets/trellisboard.py | 72 +++++++++++----------------- 1 file changed, 27 insertions(+), 45 deletions(-) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index c938db4..06d3f71 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -13,6 +13,7 @@ from litex_boards.platforms import trellisboard from litex.build.lattice.trellis import trellis_args, trellis_argdict from litex.soc.cores.clock import * +from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -20,7 +21,6 @@ from litedram.modules import MT41J256M16 from litedram.phy import ECP5DDRPHY from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -78,8 +78,8 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ -class BaseSoC(SoCSDRAM): - def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): +class BaseSoC(SoCCore): + def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", with_ethernet=False, **kwargs): platform = trellisboard.Platform(toolchain=toolchain) # SoCSDRAM --------------------------------------------------------------------------------- @@ -89,48 +89,29 @@ class BaseSoC(SoCSDRAM): self.submodules.crg = _CRG(platform, sys_clk_freq) # DDR3 SDRAM ------------------------------------------------------------------------------- - self.submodules.ddrphy = ECP5DDRPHY( - platform.request("ddram"), - sys_clk_freq=sys_clk_freq) - self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) - self.comb += self.crg.stop.eq(self.ddrphy.init.stop) - sdram_module = MT41J256M16(sys_clk_freq, "1:2") - self.register_sdram(self.ddrphy, - geom_settings = sdram_module.geom_settings, - timing_settings = sdram_module.timing_settings) - -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, toolchain="trellis", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, **kwargs) + if not self.integrated_main_ram_size: + self.submodules.ddrphy = ECP5DDRPHY( + platform.request("ddram"), + sys_clk_freq=sys_clk_freq) + self.add_csr("ddrphy") + self.add_constant("ECP5DDRPHY", None) + self.add_sdram("sdram", + phy = self.ddrphy, + module = MT41J256M16(sys_clk_freq, "1:2"), + origin = self.mem_map["main_ram"], + size = kwargs.get("max_sdram_size", 0x40000000), + l2_cache_size = kwargs.get("l2_size", 8192), + l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), + l2_cache_reverse = True + ) # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -147,8 +128,9 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), + with_ethernet=args.with_ethernet, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs) From f021c1de5f7aafe02a0741b7fbd0b2dd0d1563d9 Mon Sep 17 00:00:00 2001 From: Gabriel Somlo Date: Thu, 19 Mar 2020 22:14:54 -0400 Subject: [PATCH 3/3] targets/trellisboard: add '--with-spi-sdcard' build option Signed-off-by: Gabriel Somlo --- litex_boards/targets/trellisboard.py | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index 06d3f71..d3f44e7 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -126,11 +126,15 @@ def main(): help="system clock frequency (default=75MHz)") parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") + parser.add_argument("--with-spi-sdcard", action="store_true", + help="enable SPI-mode SDCard support") args = parser.parse_args() soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) + if args.with_spi_sdcard: + soc.add_spi_sdcard() builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs)