diff --git a/litex_boards/platforms/machdyne_kopflos.py b/litex_boards/platforms/machdyne_kopflos.py
index 859d744..541cdfa 100644
--- a/litex_boards/platforms/machdyne_kopflos.py
+++ b/litex_boards/platforms/machdyne_kopflos.py
@@ -76,10 +76,10 @@ _io_vx = [
         IOStandard("LVCMOS33")
     ),
     ("eth", 0,
-        Subsignal("rx_data", Pins("N1 P2")),
+        Subsignal("rx_data", Pins("N1 P2"), Misc("PULLMODE=UP")),
         Subsignal("tx_data", Pins("T2 R2")),
         Subsignal("tx_en", Pins("P3")),
-        Subsignal("crs_dv", Pins("M3")),
+        Subsignal("crs_dv", Pins("M3"), Misc("PULLMODE=UP")),
         Subsignal("rst_n", Pins("N4")),
         IOStandard("LVCMOS33")
     ),
diff --git a/litex_boards/targets/machdyne_kopflos.py b/litex_boards/targets/machdyne_kopflos.py
index 457371c..f37c53e 100755
--- a/litex_boards/targets/machdyne_kopflos.py
+++ b/litex_boards/targets/machdyne_kopflos.py
@@ -151,7 +151,6 @@ class BaseSoC(SoCCore):
                 clock_pads = platform.request("eth_clocks"),
                 pads = platform.request("eth"),
                 with_hw_init_reset=True,
-                hw_init_mode_cfg=[1,1,1],
                 refclk_cd=None)
             self.add_ethernet(phy=self.ethphy)