From 18337cdf258bad3c403234e5d42e2cc70ba06e56 Mon Sep 17 00:00:00 2001 From: Robert Winkler Date: Fri, 4 Dec 2020 10:28:01 +0100 Subject: [PATCH] targets/arty: sync with litex repository Signed-off-by: Robert Winkler --- litex_boards/platforms/arty.py | 5 +++-- litex_boards/targets/arty.py | 28 +++++++++++++++++----------- 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/litex_boards/platforms/arty.py b/litex_boards/platforms/arty.py index b6dee75..e0d9a90 100644 --- a/litex_boards/platforms/arty.py +++ b/litex_boards/platforms/arty.py @@ -312,12 +312,12 @@ class Platform(XilinxPlatform): default_clk_name = "clk100" default_clk_period = 1e9/100e6 - def __init__(self, variant="a7-35"): + def __init__(self, variant="a7-35", toolchain="vivado"): device = { "a7-35": "xc7a35ticsg324-1L", "a7-100": "xc7a100tcsg324-1" }[variant] - XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado") + XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"] self.toolchain.additional_commands = \ @@ -331,4 +331,5 @@ class Platform(XilinxPlatform): def do_finalize(self, fragment): XilinxPlatform.do_finalize(self, fragment) + from litex.build.xilinx import symbiflow self.add_period_constraint(self.lookup_request("clk100", loose=True), 1e9/100e6) diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 1e9ea3d..40270ef 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -4,6 +4,7 @@ # This file is part of LiteX-Boards. # # Copyright (c) 2015-2019 Florent Kermarrec +# Copyright (c) 2020 Antmicro # SPDX-License-Identifier: BSD-2-Clause import os @@ -54,13 +55,13 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs): - platform = arty.Platform() + def __init__(self, toolchain="vivado", sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, ident_version=True, **kwargs): + platform = arty.Platform(toolchain=toolchain) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, ident = "LiteX SoC on Arty A7", - ident_version = True, + ident_version = ident_version, **kwargs) # CRG -------------------------------------------------------------------------------------- @@ -104,13 +105,15 @@ class BaseSoC(SoCCore): def main(): parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7") - parser.add_argument("--build", action="store_true", help="Build bitstream") - parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") - parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") - parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") - parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") - parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--toolchain", default="vivado", help="Toolchain use to build (default: vivado)") + parser.add_argument("--build", action="store_true", help="Build bitstream") + parser.add_argument("--load", action="store_true", help="Load bitstream") + parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") + parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support") + parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support") + parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support") + parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") + parser.add_argument("--no-ident-version", action="store_false", help="Disable build time output") builder_args(parser) soc_sdram_args(parser) vivado_build_args(parser) @@ -118,9 +121,11 @@ def main(): assert not (args.with_ethernet and args.with_etherbone) soc = BaseSoC( + toolchain = args.toolchain, sys_clk_freq = int(float(args.sys_clk_freq)), with_ethernet = args.with_ethernet, with_etherbone = args.with_etherbone, + ident_version = args.no_ident_version, **soc_sdram_argdict(args) ) assert not (args.with_spi_sdcard and args.with_sdcard) @@ -130,7 +135,8 @@ def main(): if args.with_sdcard: soc.add_sdcard() builder = Builder(soc, **builder_argdict(args)) - builder.build(**vivado_build_argdict(args), run=args.build) + builder_kwargs = vivado_build_argdict(args) if args.toolchain == "vivado" else {} + builder.build(**builder_kwargs, run=args.build) if args.load: prog = soc.platform.create_programmer()