From 353aba0359e72c7fc942a387622ed3bc4ec065f3 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 21 Apr 2022 15:43:50 +0200 Subject: [PATCH] targets: Move USB-ACM/ValentyUSB clone directly to LiteX to avoid duplication in targets. --- litex_boards/targets/gsd_orangecrab.py | 10 +++------- litex_boards/targets/kosagi_fomu.py | 5 +---- litex_boards/targets/logicbone.py | 9 +++------ 3 files changed, 7 insertions(+), 17 deletions(-) diff --git a/litex_boards/targets/gsd_orangecrab.py b/litex_boards/targets/gsd_orangecrab.py index 16caf0b..3cbbc72 100755 --- a/litex_boards/targets/gsd_orangecrab.py +++ b/litex_boards/targets/gsd_orangecrab.py @@ -149,16 +149,12 @@ class BaseSoC(SoCCore): platform = orangecrab.Platform(revision=revision, device=device ,toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- - with_usb_pll = kwargs.get("uart_name") in ["serial", "usb_acm"] crg_cls = _CRGSDRAM if kwargs.get("integrated_main_ram_size", 0) == 0 else _CRG - self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll) + self.submodules.crg = crg_cls(platform, sys_clk_freq, with_usb_pll=True) # SoCCore ---------------------------------------------------------------------------------- - if kwargs["uart_name"] in ["serial"]: - kwargs["uart_name"] = "usb_acm" - # Defaults to USB ACM through ValentyUSB. - os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") - sys.path.append("valentyusb") + # Defaults to USB ACM through ValentyUSB. + kwargs["uart_name"] = "usb_acm" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on OrangeCrab", **kwargs) # DDR3 SDRAM ------------------------------------------------------------------------------- diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py index 3ba6a01..1e56c43 100755 --- a/litex_boards/targets/kosagi_fomu.py +++ b/litex_boards/targets/kosagi_fomu.py @@ -75,11 +75,8 @@ class BaseSoC(SoCCore): self.submodules.crg = _CRG(platform, sys_clk_freq) # SoCCore ---------------------------------------------------------------------------------- - # Enforce UART to USB-ACM + # Defaults to USB ACM through ValentyUSB. kwargs["uart_name"] = "usb_acm" - # FIXME: do proper install of ValentyUSB. - os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") - sys.path.append("valentyusb") # Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM. kwargs["integrated_sram_size"] = 0 kwargs["integrated_rom_size"] = 0 diff --git a/litex_boards/targets/logicbone.py b/litex_boards/targets/logicbone.py index 71aa864..be8b1fb 100755 --- a/litex_boards/targets/logicbone.py +++ b/litex_boards/targets/logicbone.py @@ -99,14 +99,11 @@ class BaseSoC(SoCCore): platform = logicbone.Platform(revision=revision, device=device ,toolchain=toolchain) # CRG -------------------------------------------------------------------------------------- - with_usb_pll = kwargs.get("uart_name", None) == "usb_acm" - self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll) + self.submodules.crg = _CRG(platform, sys_clk_freq, with_usb_pll=True) # SoCCore ---------------------------------------------------------------------------------- - if kwargs["uart_name"] == "usb_acm": - # FIXME: do proper install of ValentyUSB. - os.system("git clone https://github.com/litex-hub/valentyusb -b hw_cdc_eptri") - sys.path.append("valentyusb") + # Defaults to USB ACM through ValentyUSB. + kwargs["uart_name"] = "usb_acm" SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Logicbone", **kwargs) # DDR3 SDRAM -------------------------------------------------------------------------------