diff --git a/litex_boards/targets/1bitsquared_icebreaker.py b/litex_boards/targets/1bitsquared_icebreaker.py
index 0dd889e..835b865 100755
--- a/litex_boards/targets/1bitsquared_icebreaker.py
+++ b/litex_boards/targets/1bitsquared_icebreaker.py
@@ -98,7 +98,6 @@ class BaseSoC(SoCCore):
         from litespi.modules import W25Q128JV
         from litespi.opcodes import SpiNorFlashOpCodes as Codes
         self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
-        #self.add_spi_flash(mode="1x", dummy_cycles=8) # LiteX SPI Flash Core.
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
diff --git a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
index beed298..5147529 100755
--- a/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
+++ b/litex_boards/targets/1bitsquared_icebreaker_bitsy.py
@@ -93,7 +93,6 @@ class BaseSoC(SoCCore):
         from litespi.modules import W25Q128JV
         from litespi.opcodes import SpiNorFlashOpCodes as Codes
         self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=False)
-        #self.add_spi_flash(mode="1x", dummy_cycles=8) # LiteX SPI Flash Core.
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(
diff --git a/litex_boards/targets/kosagi_fomu.py b/litex_boards/targets/kosagi_fomu.py
index 05751c8..660542e 100755
--- a/litex_boards/targets/kosagi_fomu.py
+++ b/litex_boards/targets/kosagi_fomu.py
@@ -111,7 +111,6 @@ class BaseSoC(SoCCore):
             "W25Q128JV":  lambda: W25Q128JV( Codes.READ_1_1_4),
         }
         self.add_spi_flash(mode="4x", module=spi_flash_modules[spi_flash_module](), with_master=False)
-        #self.add_spi_flash(mode="1x", dummy_cycles=8) # LiteX SPI Flash Core.
 
         # Add ROM linker region --------------------------------------------------------------------
         self.bus.add_region("rom", SoCRegion(