From 3730d96709c93d2156cdd940a326e28f9f93eb31 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 15 Oct 2021 18:21:21 +0200
Subject: [PATCH] litex_acorn_baseboard: Add SPIFlash support.
---
litex_boards/platforms/litex_acorn_baseboard.py | 8 ++++++++
litex_boards/targets/litex_acorn_baseboard.py | 11 ++++++++++-
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/litex_boards/platforms/litex_acorn_baseboard.py b/litex_boards/platforms/litex_acorn_baseboard.py
index 7ad5101..c54ecc4 100644
--- a/litex_boards/platforms/litex_acorn_baseboard.py
+++ b/litex_boards/platforms/litex_acorn_baseboard.py
@@ -34,6 +34,14 @@ _io = [
IOStandard("LVCMOS33")
),
+ # SPIFlash
+ ("spiflash4x", 0,
+ Subsignal("cs_n", Pins("R2")),
+ #Subsignal("clk", Pins("U3")),
+ Subsignal("dq", Pins("W2 V2 Y2 W1")),
+ IOStandard("LVCMOS33")
+ ),
+
# RGMII Ethernet
("eth_clocks", 0,
Subsignal("tx", Pins("M1")),
diff --git a/litex_boards/targets/litex_acorn_baseboard.py b/litex_boards/targets/litex_acorn_baseboard.py
index f570020..6bb067d 100755
--- a/litex_boards/targets/litex_acorn_baseboard.py
+++ b/litex_boards/targets/litex_acorn_baseboard.py
@@ -64,6 +64,7 @@ class _CRG(Module):
class BaseSoC(SoCCore):
def __init__(self, sys_clk_freq=int(75e6),
+ with_spi_flash = False,
with_ethernet = False,
with_etherbone = False,
with_video_terminal = False,
@@ -80,6 +81,12 @@ class BaseSoC(SoCCore):
# CRG --------------------------------------------------------------------------------------
self.submodules.crg = _CRG(platform, sys_clk_freq, with_video_pll=with_video_terminal)
+ # SPI Flash --------------------------------------------------------------------------------
+ if with_spi_flash:
+ from litespi.modules import W25Q128JV
+ from litespi.opcodes import SpiNorFlashOpCodes as Codes
+ self.add_spi_flash(mode="4x", module=W25Q128JV(Codes.READ_1_1_4), with_master=True)
+
# Ethernet / Etherbone ---------------------------------------------------------------------
if with_ethernet or with_etherbone:
self.submodules.ethphy = LiteEthPHYRGMII(
@@ -119,7 +126,8 @@ def main():
sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
viopts = parser.add_mutually_exclusive_group()
viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI)")
- parser.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support")
+ parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
+ parser.add_argument("--with-lcd", action="store_true", help="Enable OLED LCD support")
builder_args(parser)
soc_core_args(parser)
@@ -128,6 +136,7 @@ def main():
soc = BaseSoC(
sys_clk_freq = int(float(args.sys_clk_freq)),
+ with_spi_flash = args.with_spi_flash,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_video_terminal = args.with_video_terminal,