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Merge pull request #614 from pepijndevos/tec0117apicula 

Update tec0117 to work with Apicula
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Gwenhael Goavec-Merou 2024-10-05 07:05:50 +02:00 committed by GitHub
parent 7f3ee12c3d 9d68972fa8
commit 3742a25233
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GPG Key ID: B5690EEEBB952194
1 changed files with 22 additions and 18 deletions
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40
litex_boards/targets/trenz_tec0117.py
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@ -28,7 +28,7 @@ from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(LiteXModule): class _CRG(LiteXModule):
def __init__(self, platform, sys_clk_freq): def __init__(self, platform, sys_clk_freq, sdram_rate):
self.rst = Signal() self.rst = Signal()
self.cd_sys = ClockDomain() self.cd_sys = ClockDomain()
self.cd_sys2x = ClockDomain() self.cd_sys2x = ClockDomain()
@ -43,25 +43,28 @@ class _CRG(LiteXModule):
self.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device) self.pll = pll = GW1NPLL(devicename=platform.devicename, device=platform.device)
self.comb += pll.reset.eq(~rst_n) self.comb += pll.reset.eq(~rst_n)
pll.register_clkin(clk100, 100e6) pll.register_clkin(clk100, 100e6)
pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq, with_reset=False) if sdram_rate == "1:2":
self.specials += Instance("CLKDIV", pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq, with_reset=False)
p_DIV_MODE= "2", self.specials += Instance("CLKDIV",
i_RESETN = rst_n, p_DIV_MODE= "2",
i_HCLKIN = self.cd_sys2x.clk, i_RESETN = rst_n,
o_CLKOUT = self.cd_sys.clk i_HCLKIN = self.cd_sys2x.clk,
) o_CLKOUT = self.cd_sys.clk
)
else:
pll.create_clkout(self.cd_sys, sys_clk_freq, with_reset=False)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n) self.specials += AsyncResetSynchronizer(self.cd_sys, ~rst_n)
# BaseSoC ------------------------------------------------------------------------------------------ # BaseSoC ------------------------------------------------------------------------------------------
class BaseSoC(SoCCore): class BaseSoC(SoCCore):
def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=25e6, sdram_rate="1:1", def __init__(self, bios_flash_offset=0x0000, sys_clk_freq=25e6, sdram_rate="1:1",
with_led_chaser = True, with_led_chaser = True, toolchain="gowin",
**kwargs): **kwargs):
platform = trenz_tec0117.Platform() platform = trenz_tec0117.Platform(toolchain=toolchain)
# CRG -------------------------------------------------------------------------------------- # CRG --------------------------------------------------------------------------------------
self.crg = _CRG(platform, sys_clk_freq) self.crg = _CRG(platform, sys_clk_freq, sdram_rate)
# SoCCore ---------------------------------------------------------------------------------- # SoCCore ----------------------------------------------------------------------------------
# Disable Integrated ROM. # Disable Integrated ROM.
@ -116,10 +119,10 @@ class BaseSoC(SoCCore):
# Flash -------------------------------------------------------------------------------------------- # Flash --------------------------------------------------------------------------------------------
def flash(bios_flash_offset): def flash(bios_flash_offset, toolchain="gowin"):
# Create FTDI <--> SPI Flash proxy bitstream and load it. # Create FTDI <--> SPI Flash proxy bitstream and load it.
# ------------------------------------------------------- # -------------------------------------------------------
platform = trenz_tec0117.Platform() platform = trenz_tec0117.Platform(toolchain=toolchain)
flash = platform.request("spiflash", 0) flash = platform.request("spiflash", 0)
bus = platform.request("spiflash", 1) bus = platform.request("spiflash", 1)
module = Module() module = Module()
@ -131,9 +134,9 @@ def flash(bios_flash_offset):
] ]
platform.build(module) platform.build(module)
prog = platform.create_programmer() prog = platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs")) # FIXME prog.flash(0, "build/top.fs")
# Flash Image through proxy Bitstream. # Flash Image through proxy Bitstream using pyspiflash
# ------------------------------------ # ------------------------------------
from spiflash.serialflash import SerialFlashManager from spiflash.serialflash import SerialFlashManager
dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2") dev = SerialFlashManager.get_flash_device("ftdi://ftdi:2232/2")
@ -161,6 +164,7 @@ def main():
soc = BaseSoC( soc = BaseSoC(
bios_flash_offset = int(args.bios_flash_offset, 0), bios_flash_offset = int(args.bios_flash_offset, 0),
sys_clk_freq = args.sys_clk_freq, sys_clk_freq = args.sys_clk_freq,
toolchain = args.toolchain,
**parser.soc_argdict **parser.soc_argdict
) )
soc.platform.add_extension(trenz_tec0117._sdcard_pmod_io) soc.platform.add_extension(trenz_tec0117._sdcard_pmod_io)
@ -175,12 +179,12 @@ def main():
if args.load: if args.load:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="sram")) prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
if args.flash: if args.flash:
prog = soc.platform.create_programmer() prog = soc.platform.create_programmer()
prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs")) # FIXME flash(int(args.bios_flash_offset, 0), toolchain=args.toolchain)
flash(int(args.bios_flash_offset, 0)) prog.flash(0, builder.get_bitstream_filename(mode="flash", ext=".fs"))
if __name__ == "__main__": if __name__ == "__main__":
main() main()