From 376a83658322e2cb43b474893b87d364b5bef057 Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 17 Sep 2021 15:57:55 +0200
Subject: [PATCH] sipeed_tang_nano: Add SPI Flash, Enable CPU and use new
 external SPI Flash support from OpenFPGALoader.

./sipeed_tang_nano_4k.py --cpu-type=vexriscv --cpu-variant=lite --build --flash

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2021 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Sep 17 2021 15:54:08
 BIOS CRC passed (6cc6de6d)

 Migen git sha1: a5bc262
 LiteX git sha1: 46cd9c5a

--=============== SoC ==================--
CPU:		VexRiscv_Lite @ 27MHz
BUS:		WISHBONE 32-bit @ 4GiB
CSR:		32-bit data
ROM:		64KiB
SRAM:		8KiB
FLASH:		4096KiB

--========== Initialization ============--

Initializing W25Q32 SPI Flash @0x80000000...
SPI Flash clk configured to 13 MHz
Memspeed at 0x80000000 (Sequential, 4.0KiB)...
   Read speed: 1.3MiB/s
Memspeed at 0x80000000 (Random, 4.0KiB)...
   Read speed: 521.9KiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found

--============= Console ================--

litex>
---
 litex_boards/platforms/sipeed_tang_nano_4k.py |  7 ++++++
 litex_boards/targets/sipeed_tang_nano_4k.py   | 25 ++++++++++++++++---
 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/litex_boards/platforms/sipeed_tang_nano_4k.py b/litex_boards/platforms/sipeed_tang_nano_4k.py
index a80e632..1dfcf87 100644
--- a/litex_boards/platforms/sipeed_tang_nano_4k.py
+++ b/litex_boards/platforms/sipeed_tang_nano_4k.py
@@ -28,6 +28,13 @@ _io = [
     ("user_btn", 0, Pins("14"),  IOStandard("LVCMOS18")),
     ("user_btn", 1, Pins("15"),  IOStandard("LVCMOS18")),
 
+    # Serial (FIXME: For tests, change or remove.)
+    ("serial", 0,
+        Subsignal("rx", Pins("44")), # CAM_SCL
+        Subsignal("tx", Pins("46")), # CAM_SDA
+        IOStandard("LVCMOS33")
+    ),
+
     # SPIFlash
     ("spiflash", 0,
         Subsignal("cs_n", Pins("2"), IOStandard("LVCMOS33")),
diff --git a/litex_boards/targets/sipeed_tang_nano_4k.py b/litex_boards/targets/sipeed_tang_nano_4k.py
index 2172861..9362074 100755
--- a/litex_boards/targets/sipeed_tang_nano_4k.py
+++ b/litex_boards/targets/sipeed_tang_nano_4k.py
@@ -13,11 +13,15 @@ from migen import *
 from migen.genlib.resetsync import AsyncResetSynchronizer
 
 from litex.soc.integration.soc_core import *
+from litex.soc.integration.soc import SoCRegion
 from litex.soc.integration.builder import *
 from litex.soc.cores.led import LedChaser
 
 from litex_boards.platforms import tang_nano_4k
 
+kB = 1024
+mB = 1024*kB
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -36,13 +40,13 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
+    mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
     def __init__(self, sys_clk_freq=int(27e6), with_led_chaser=True, **kwargs):
         platform = tang_nano_4k.Platform()
 
-
-        # Disable CPU/UART for now.
-        kwargs["cpu_type"]  = None
-        kwargs["with_uart"] = False
+        # Put BIOS in SPIFlash to save BlockRAMs.
+        kwargs["integrated_rom_size"] = 0
+        kwargs["cpu_reset_address"]   = self.mem_map["spiflash"] + 0
 
         # SoCCore ----------------------------------------------------------------------------------
         SoCCore.__init__(self, platform, sys_clk_freq,
@@ -53,6 +57,18 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
 
+        # SPI Flash --------------------------------------------------------------------------------
+        from litespi.modules import W25Q32
+        from litespi.opcodes import SpiNorFlashOpCodes as Codes
+        self.add_spi_flash(mode="1x", module=W25Q32(Codes.READ_1_1_1), with_master=False)
+
+        # Add ROM linker region --------------------------------------------------------------------
+        self.bus.add_region("rom", SoCRegion(
+            origin = self.mem_map["spiflash"] + 0,
+            size   = 64*kB,
+            linker = True)
+        )
+
         # Leds -------------------------------------------------------------------------------------
         if with_led_chaser:
             self.submodules.leds = LedChaser(
@@ -86,6 +102,7 @@ def main():
     if args.flash:
         prog = soc.platform.create_programmer()
         prog.flash(0, os.path.join(builder.gateware_dir, "impl", "pnr", "project.fs"))
+        prog.flash(0, "build/sipeed_tang_nano_4k/software/bios/bios.bin", external=True)
 
 if __name__ == "__main__":
     main()