From 38bff921b214045be21bb4332e0a9c4e4e6cfd5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bastian=20L=C3=B6her?= Date: Sun, 16 Jan 2022 13:00:46 +0100 Subject: [PATCH] Fixup. --- litex_boards/platforms/digilent_cmod_a7.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index 09e1280..476610c 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -65,10 +65,11 @@ class Platform(XilinxPlatform): def __init__(self, variant="a7-35", toolchain="vivado"): device = { - "a7-35": "xc7a35t-cpg236-1" + "a7-35": "xc7a35tcpg236-1" }[variant] XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain) def do_finalize(self,fragment): XilinxPlatform.do_finalize(self, fragment) + from litex.build.xilinx import symbiflow self.add_period_constraint(self.lookup_request("clk12", loose=True), self.default_clk_period)