From a6b025f7f3e8210a84d7987a740001bf3df420ba Mon Sep 17 00:00:00 2001 From: Bayi Date: Sat, 5 Aug 2023 19:56:15 +0200 Subject: [PATCH 1/2] Fix Digilent Cmod A7 ISSIRAM reading --- litex_boards/platforms/digilent_cmod_a7.py | 1 + litex_boards/targets/digilent_cmod_a7.py | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/litex_boards/platforms/digilent_cmod_a7.py b/litex_boards/platforms/digilent_cmod_a7.py index 521eaaa..56976d8 100644 --- a/litex_boards/platforms/digilent_cmod_a7.py +++ b/litex_boards/platforms/digilent_cmod_a7.py @@ -49,6 +49,7 @@ _io = [ IOStandard("LVCMOS33")), Subsignal("wen", Pins("R19"), IOStandard("LVCMOS33")), Subsignal("cen", Pins("N19"), IOStandard("LVCMOS33")), + Subsignal("oe", Pins("P19"), IOStandard("LVCMOS33")), Misc("SLEW=FAST"), ), diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 291b22f..3216e17 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -70,7 +70,8 @@ class AsyncSRAM(LiteXModule): self.comb += [ cen.eq(~chip_ena), wen.eq(~write_ena), - tristate_data.oe.eq(write_ena) + tristate_data.oe.eq(write_ena), + oe.eq(tristate_data.oe), ] ######################## # address and data From 4362cb23a18eb433c627f2ae72a8411e2e1f5f87 Mon Sep 17 00:00:00 2001 From: Bayi Date: Sat, 5 Aug 2023 19:56:32 +0200 Subject: [PATCH 2/2] Fix Digilent Cmod A7 ISSIRAM reading --- litex_boards/targets/digilent_cmod_a7.py | 1 + 1 file changed, 1 insertion(+) diff --git a/litex_boards/targets/digilent_cmod_a7.py b/litex_boards/targets/digilent_cmod_a7.py index 3216e17..a9852e5 100755 --- a/litex_boards/targets/digilent_cmod_a7.py +++ b/litex_boards/targets/digilent_cmod_a7.py @@ -56,6 +56,7 @@ class AsyncSRAM(LiteXModule): data = issiram.data wen = issiram.wen cen = issiram.cen + oe = issiram.oe ######################## tristate_data = TSTriple(data_width) self.specials += tristate_data.get_tristate(data)