From 3b91e96c42a6e9a698a0ef01693fcca4a2a137a8 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Thu, 26 Mar 2020 09:46:29 +0100 Subject: [PATCH] targets/add_constant: avoid specifying value when value is None (=default) --- litex_boards/targets/camlink_4k.py | 2 +- litex_boards/targets/kcu105.py | 4 ++-- litex_boards/targets/mercury_xu5.py | 4 ++-- litex_boards/targets/orangecrab.py | 2 +- litex_boards/targets/trellisboard.py | 2 +- litex_boards/targets/vcu118.py | 4 ++-- litex_boards/targets/versa_ecp5.py | 2 +- litex_boards/targets/zcu104.py | 4 ++-- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/litex_boards/targets/camlink_4k.py b/litex_boards/targets/camlink_4k.py index e024c44..d058b65 100755 --- a/litex_boards/targets/camlink_4k.py +++ b/litex_boards/targets/camlink_4k.py @@ -85,7 +85,7 @@ class BaseSoC(SoCCore): platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) + self.add_constant("ECP5DDRPHY") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index d9dfb4f..964853f 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -67,8 +67,8 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 200e6, cmd_latency = 0) self.add_csr("ddrphy") - self.add_constant("USDDRPHY", None) - self.add_constant("USDDRPHY_DEBUG", None) + self.add_constant("USDDRPHY") + self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), diff --git a/litex_boards/targets/mercury_xu5.py b/litex_boards/targets/mercury_xu5.py index 8e4bb64..3b777f0 100755 --- a/litex_boards/targets/mercury_xu5.py +++ b/litex_boards/targets/mercury_xu5.py @@ -66,8 +66,8 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 500e6, cmd_latency = 0) self.add_csr("ddrphy") - self.add_constant("USDDRPHY", None) - self.add_constant("USDDRPHY_DEBUG", None) + self.add_constant("USDDRPHY") + self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = MT40A256M16(sys_clk_freq, "1:4"), diff --git a/litex_boards/targets/orangecrab.py b/litex_boards/targets/orangecrab.py index b49d6fb..824897e 100755 --- a/litex_boards/targets/orangecrab.py +++ b/litex_boards/targets/orangecrab.py @@ -116,7 +116,7 @@ class BaseSoC(SoCCore): platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) + self.add_constant("ECP5DDRPHY") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/trellisboard.py b/litex_boards/targets/trellisboard.py index dde153a..aca628c 100755 --- a/litex_boards/targets/trellisboard.py +++ b/litex_boards/targets/trellisboard.py @@ -94,7 +94,7 @@ class BaseSoC(SoCCore): platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) + self.add_constant("ECP5DDRPHY") self.add_sdram("sdram", phy = self.ddrphy, module = MT41J256M16(sys_clk_freq, "1:2"), diff --git a/litex_boards/targets/vcu118.py b/litex_boards/targets/vcu118.py index 26051a7..87738f9 100755 --- a/litex_boards/targets/vcu118.py +++ b/litex_boards/targets/vcu118.py @@ -66,8 +66,8 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 500e6, cmd_latency = 0) self.add_csr("ddrphy") - self.add_constant("USDDRPHY", None) - self.add_constant("USDDRPHY_DEBUG", None) + self.add_constant("USDDRPHY") + self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = EDY4016A(sys_clk_freq, "1:4"), diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index 9991a81..0e93073 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -87,7 +87,7 @@ class BaseSoC(SoCCore): platform.request("ddram"), sys_clk_freq=sys_clk_freq) self.add_csr("ddrphy") - self.add_constant("ECP5DDRPHY", None) + self.add_constant("ECP5DDRPHY") self.comb += self.crg.stop.eq(self.ddrphy.init.stop) self.add_sdram("sdram", phy = self.ddrphy, diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 80f091a..da55f2c 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -65,8 +65,8 @@ class BaseSoC(SoCCore): iodelay_clk_freq = 500e6, cmd_latency = 1) self.add_csr("ddrphy") - self.add_constant("USDDRPHY", None) - self.add_constant("USDDRPHY_DEBUG", None) + self.add_constant("USDDRPHY") + self.add_constant("USDDRPHY_DEBUG") self.add_sdram("sdram", phy = self.ddrphy, module = KVR21SE15S84(sys_clk_freq, "1:4"),