From 7a911b8ff664f0fe5846b57b0149373b063c64d3 Mon Sep 17 00:00:00 2001 From: Luc Lagarde Date: Fri, 6 Jan 2023 16:09:56 -0600 Subject: [PATCH] Allow building digilent_arty using f4pga Only use XADC() and DNA() functions if vivado is the current toolchain. --- litex_boards/targets/digilent_arty.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/litex_boards/targets/digilent_arty.py b/litex_boards/targets/digilent_arty.py index ca155a0..dd44981 100755 --- a/litex_boards/targets/digilent_arty.py +++ b/litex_boards/targets/digilent_arty.py @@ -91,11 +91,13 @@ class BaseSoC(SoCCore): SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC on Arty A7", **kwargs) # XADC ------------------------------------------------------------------------------------- - self.xadc = XADC() + if toolchain == "vivado": + self.xadc = XADC() # DNA -------------------------------------------------------------------------------------- - self.dna = DNA() - self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) + if toolchain == "vivado": + self.dna = DNA() + self.dna.add_timing_constraints(platform, sys_clk_freq, self.crg.cd_sys.clk) # DDR3 SDRAM ------------------------------------------------------------------------------- if not self.integrated_main_ram_size: