diff --git a/litex_boards/platforms/qmtech_10cl006.py b/litex_boards/platforms/qmtech_10cl006.py index 7f669ed..7a882df 100644 --- a/litex_boards/platforms/qmtech_10cl006.py +++ b/litex_boards/platforms/qmtech_10cl006.py @@ -18,13 +18,6 @@ _io = [ ("key", 0, Pins("F3"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("J6"), IOStandard("3.3-V LVTTL")), - # Serial - ("serial", 0, - # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) - Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10) - Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) - ), - # SPIFlash (W25Q64) ("spiflash", 0, # clk @@ -128,7 +121,14 @@ _connectors = [ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - core_resources = [ ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")) ] + core_resources = [ + ("user_led", 0, Pins("L9"), IOStandard("3.3-V LVTTL")), + ("serial", 0, + # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) + Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10) + Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) + ), + ] def __init__(self, with_daughterboard=False): device = "10CL006YU256C8G" diff --git a/litex_boards/platforms/qmtech_5cefa2.py b/litex_boards/platforms/qmtech_5cefa2.py index d52953e..d886162 100644 --- a/litex_boards/platforms/qmtech_5cefa2.py +++ b/litex_boards/platforms/qmtech_5cefa2.py @@ -18,12 +18,6 @@ _io = [ ("key", 0, Pins("AB13"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("V18"), IOStandard("3.3-V LVTTL")), - # Serial - ("serial", 0, - Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")), - Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL")) - ), - # SPIFlash (MT25QL128ABA) ("spiflash", 0, # clk @@ -127,7 +121,13 @@ _connectors = [ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - core_resources = [ ("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")) ] + core_resources = [ + ("user_led", 0, Pins("D17"), IOStandard("3.3-V LVTTL")), + ("serial", 0, + Subsignal("tx", Pins("J3:8"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("J3:7"), IOStandard("3.3-V LVTTL")) + ), + ] def __init__(self, with_daughterboard=False): device = "5CEFA2F23C8" @@ -145,7 +145,7 @@ class Platform(AlteraPlatform): AlteraPlatform.__init__(self, device, io, connectors) if with_daughterboard: - # an ethernet pin takes the config pin, so make it available + # ethernet takes the config pin, so make it available self.add_platform_command("set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION \"USE AS REGULAR IO\"") # Generate PLL clock in STA diff --git a/litex_boards/platforms/qmtech_daughterboard.py b/litex_boards/platforms/qmtech_daughterboard.py index ef49df2..7c06e7a 100644 --- a/litex_boards/platforms/qmtech_daughterboard.py +++ b/litex_boards/platforms/qmtech_daughterboard.py @@ -77,7 +77,6 @@ class QMTechDaughterboard: Subsignal("cmd", Pins("J3:12")), Subsignal("clk", Pins("J3:11")), Subsignal("cd", Pins("J3:8")), - Misc("SLEW=FAST"), io_standard, ), ] diff --git a/litex_boards/platforms/qmtech_ep4ce15.py b/litex_boards/platforms/qmtech_ep4ce15.py index 36d0c38..cb51234 100644 --- a/litex_boards/platforms/qmtech_ep4ce15.py +++ b/litex_boards/platforms/qmtech_ep4ce15.py @@ -19,13 +19,6 @@ _io = [ ("key", 0, Pins("Y13"), IOStandard("3.3-V LVTTL")), ("key", 1, Pins("W13"), IOStandard("3.3-V LVTTL")), - # Serial - ("serial", 0, - # Compatible with cheap FT232 based cables (ex: Gaoominy 6Pin Ftdi Ft232Rl Ft232) - Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), # GPIO_07 (JP1 Pin 10) - Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) # GPIO_05 (JP1 Pin 8) - ), - # SPIFlash (W25Q64) ("spiflash", 0, # clk @@ -129,7 +122,13 @@ _connectors = [ class Platform(AlteraPlatform): default_clk_name = "clk50" default_clk_period = 1e9/50e6 - core_resources = [ ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")) ] + core_resources = [ + ("user_led", 0, Pins("E4"), IOStandard("3.3-V LVTTL")), + ("serial", 0, + Subsignal("tx", Pins("J3:7"), IOStandard("3.3-V LVTTL")), + Subsignal("rx", Pins("J3:8"), IOStandard("3.3-V LVTTL")) + ), + ] def __init__(self, with_daughterboard=False): device = "EP4CE15F23C8" diff --git a/litex_boards/targets/qmtech_10cl006.py b/litex_boards/targets/qmtech_10cl006.py index cab5013..92629da 100755 --- a/litex_boards/targets/qmtech_10cl006.py +++ b/litex_boards/targets/qmtech_10cl006.py @@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -99,7 +99,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) diff --git a/litex_boards/targets/qmtech_5cefa2.py b/litex_boards/targets/qmtech_5cefa2.py index 58e6e50..dc88b66 100755 --- a/litex_boards/targets/qmtech_5cefa2.py +++ b/litex_boards/targets/qmtech_5cefa2.py @@ -22,7 +22,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -62,7 +62,8 @@ class _CRG(Module): # theoretically 90 degrees, but increase to relax timing pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) else: - pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=90) + # for 105 MHz: 10; 95 MHz: 15; 85MHz: 30 work + pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=10) if with_ethernet: pll.create_clkout(self.cd_eth, 25e6) @@ -76,7 +77,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), with_daughterboard=False, + def __init__(self, sys_clk_freq=int(105e6), with_daughterboard=False, with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", eth_dynamic_ip=False, with_led_chaser=True, with_video_terminal=False, with_video_framebuffer=False, ident_version=True, sdram_rate="1:1", **kwargs): @@ -100,7 +101,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) ) @@ -134,7 +135,7 @@ def main(): parser = argparse.ArgumentParser(description="LiteX SoC on QMTECH 5CEFA2") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") - parser.add_argument("--sys-clk-freq", default=75e6, help="System clock frequency (default: 75MHz)") + parser.add_argument("--sys-clk-freq", default=105e6, help="System clock frequency (default: 105MHz)") parser.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate") parser.add_argument("--with-daughterboard", action="store_true", help="Whether the core board is plugged into the QMTech daughterboard") ethopts = parser.add_mutually_exclusive_group() diff --git a/litex_boards/targets/qmtech_ep4ce15.py b/litex_boards/targets/qmtech_ep4ce15.py index a91f2f4..f49a6ad 100755 --- a/litex_boards/targets/qmtech_ep4ce15.py +++ b/litex_boards/targets/qmtech_ep4ce15.py @@ -21,7 +21,7 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from litex.soc.cores.led import LedChaser -from litedram.modules import IS42S16160 +from litedram.modules import W9825G6KH6 from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY from litex.soc.cores.video import VideoVGAPHY @@ -97,7 +97,7 @@ class BaseSoC(SoCCore): self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"), sys_clk_freq) self.add_sdram("sdram", phy = self.sdrphy, - module = IS42S16160(sys_clk_freq, sdram_rate), + module = W9825G6KH6(sys_clk_freq, sdram_rate), l2_cache_size = kwargs.get("l2_size", 8192) )