From 379745b039b8ba2288d51a71bdb352c750856dd1 Mon Sep 17 00:00:00 2001 From: Franck Jullien Date: Tue, 21 Dec 2021 12:34:19 +0100 Subject: [PATCH] efinix: add clock pins to t120 bga576 platform --- litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py index ba076b6..d916308 100644 --- a/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py +++ b/litex_boards/platforms/efinix_trion_t120_bga576_dev_kit.py @@ -14,6 +14,9 @@ from litex.build.efinix import EfinixProgrammer _io = [ # Clk ("clk40", 0, Pins("P19"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), + ("clk50", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), + ("clk20", 0, Pins("AA9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), + ("clk74_25", 0, Pins("J9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), # Leds ("user_led", 0, Pins("AB16"), IOStandard("3.3_V_LVTTL_/_LVCMOS"), Misc("DRIVE_STRENGTH=3")), @@ -92,6 +95,9 @@ _io = [ # DRAM. ("dram_pll_refclk", 0, Pins("AA8"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), + + # MIPI + ("mipi_refclk", 0, Pins("G9"), IOStandard("3.3_V_LVTTL_/_LVCMOS")), ] # Bank voltage ---------------------------------------------------------------------------------------