From 3e9e9bc4257c36f720e994d4d33cb44ac14175b0 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sun, 21 Nov 2021 19:10:21 +0100 Subject: [PATCH] platforms/sqrl_acorn: Add Multiboot Operational/Fallabck bistreams generation. To allow recovery in case of PCIe update failure (Write error, power issue or crash). --- litex_boards/platforms/sqrl_acorn.py | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/litex_boards/platforms/sqrl_acorn.py b/litex_boards/platforms/sqrl_acorn.py index 1b5ffbb..2113ec1 100644 --- a/litex_boards/platforms/sqrl_acorn.py +++ b/litex_boards/platforms/sqrl_acorn.py @@ -128,9 +128,22 @@ class Platform(XilinxPlatform): "set_property CFGBVS VCCO [current_design]", "set_property CONFIG_VOLTAGE 3.3 [current_design]", ] - self.toolchain.additional_commands = \ - ["write_cfgmem -force -format bin -interface spix4 -size 16 " - "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin"] + + self.toolchain.additional_commands = [ + # Non-Multiboot SPI-Flash bitstream generation. + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.bin", + + # Multiboot SPI-Flash Operational bitstream generation. + "set_property BITSTREAM.CONFIG.TIMER_CFG 0x0001fbd0 [current_design]", + "set_property BITSTREAM.CONFIG.CONFIGFALLBACK Enable [current_design]", + "write_bitstream -force {build_name}_operational.bit ", + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_operational.bit\" -file {build_name}_operational.bin", + + # Multiboot SPI-Flash Fallback bitstream generation. + "set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0x00400000 [current_design]", + "write_bitstream -force {build_name}_fallback.bit ", + "write_cfgmem -force -format bin -interface spix4 -size 16 -loadbit \"up 0x0 {build_name}_fallback.bit\" -file {build_name}_fallback.bin" + ] def create_programmer(self, name='openocd'): if name == 'openocd':