From 3f191c85611e076b739efe8637dec932e46615d9 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 9 Mar 2020 09:28:25 +0100 Subject: [PATCH] mercury_xu5: set INTERNAL_VREF to 0.84. (similar to others Ultrascale boards with DDR4). --- litex_boards/platforms/mercury_xu5.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/mercury_xu5.py b/litex_boards/platforms/mercury_xu5.py index d2bcb28..50e5591 100644 --- a/litex_boards/platforms/mercury_xu5.py +++ b/litex_boards/platforms/mercury_xu5.py @@ -143,4 +143,4 @@ class Platform(XilinxPlatform): XilinxPlatform.do_finalize(self, fragment) self.add_platform_command("set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN ENABLE [current_design]") self.add_platform_command("set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]") - self.add_platform_command("set_property INTERNAL_VREF 0.600 [get_iobanks 64]") + self.add_platform_command("set_property INTERNAL_VREF 0.84 [get_iobanks 64]")