From 3f58df99749c24b19f7769326ff0a5865c50dcb2 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Mon, 14 Feb 2022 17:26:46 +0100 Subject: [PATCH] platforms/targets: Fix typos. --- litex_boards/platforms/digilent_zedboard.py | 2 +- litex_boards/targets/digilent_arty_z7.py | 8 ++++++-- litex_boards/targets/digilent_zedboard.py | 8 ++++++-- 3 files changed, 13 insertions(+), 5 deletions(-) diff --git a/litex_boards/platforms/digilent_zedboard.py b/litex_boards/platforms/digilent_zedboard.py index f4b2004..0f82b3a 100644 --- a/litex_boards/platforms/digilent_zedboard.py +++ b/litex_boards/platforms/digilent_zedboard.py @@ -205,7 +205,7 @@ class Platform(XilinxPlatform): default_clk_period = 1e9/100e6 def __init__(self, toolchain="vivado"): - XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchains) + XilinxPlatform.__init__(self, "xc7z020clg484-1", _io, _connectors, toolchain=toolchain) self.toolchain.bitstream_commands = \ ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", ] diff --git a/litex_boards/targets/digilent_arty_z7.py b/litex_boards/targets/digilent_arty_z7.py index e91a392..5dc297d 100755 --- a/litex_boards/targets/digilent_arty_z7.py +++ b/litex_boards/targets/digilent_arty_z7.py @@ -39,10 +39,14 @@ class _CRG(Module): self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) else: + # Clk. + clk125 = platform.request("clk125") + + # PLL. self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(self.rst) - pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq) - pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.register_clkin(clk125, 125e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) # Ignore sys_clk to pll.clkin path created by SoC's rst. platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) diff --git a/litex_boards/targets/digilent_zedboard.py b/litex_boards/targets/digilent_zedboard.py index 8b3b94b..21fa434 100755 --- a/litex_boards/targets/digilent_zedboard.py +++ b/litex_boards/targets/digilent_zedboard.py @@ -37,10 +37,14 @@ class _CRG(Module): self.comb += ClockSignal("sys").eq(ClockSignal("ps7")) self.comb += ResetSignal("sys").eq(ResetSignal("ps7") | self.rst) else: + # Clk. + clk100 = platform.request("clk100") + + # PLL. self.submodules.pll = pll = S7PLL(speedgrade=-1) self.comb += pll.reset.eq(self.rst) - pll.register_clkin(platform.request(platform.default_clk_name), platform.default_clk_freq) - pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.register_clkin(clk100, 100e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) # Ignore sys_clk to pll.clkin path created by SoC's rst. platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin)