From 3fb3ba18e880263d07f2f46fabc5cd6d23661095 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Sat, 21 Mar 2020 18:29:52 +0100 Subject: [PATCH] targets: switch to add_ethernet method instead of EthernetSoC. --- litex_boards/targets/ac701.py | 110 ++++++++++------------------ litex_boards/targets/arty.py | 47 +++--------- litex_boards/targets/c10lprefkit.py | 47 ++---------- litex_boards/targets/genesys2.py | 45 ++---------- litex_boards/targets/kc705.py | 47 +++--------- litex_boards/targets/kcu105.py | 49 +++---------- litex_boards/targets/mimas_a7.py | 43 +++-------- litex_boards/targets/netv2.py | 47 +++--------- litex_boards/targets/nexys4ddr.py | 47 +++--------- litex_boards/targets/nexys_video.py | 45 ++---------- litex_boards/targets/simple.py | 36 +++------ litex_boards/targets/versa_ecp5.py | 42 ++--------- litex_boards/targets/zcu104.py | 2 +- 13 files changed, 137 insertions(+), 470 deletions(-) diff --git a/litex_boards/targets/ac701.py b/litex_boards/targets/ac701.py index 7ca62f7..0d5808f 100755 --- a/litex_boards/targets/ac701.py +++ b/litex_boards/targets/ac701.py @@ -21,7 +21,6 @@ from litedram.phy import s7ddrphy from liteeth.phy.a7_gtp import QPLLSettings, QPLL from liteeth.phy.a7_1000basex import A7_1000BASEX from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -47,7 +46,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, ethernet_phy="rgmii", **kwargs): platform = ac701.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -73,73 +72,43 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- + # Ethernet --------------------------------------------------------------------------------- + if with_ethernet: + # RGMII Ethernet PHY ------------------------------------------------------------------- + if ethernet_phy == "rgmii": + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) + # 1000BaseX Ethernet PHY --------------------------------------------------------------- + if ethernet_phy == "1000basex": + # phy + self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) + self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) + self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) + qpll_settings = QPLLSettings( + refclksel = 0b001, + fbdiv = 4, + fbdiv_45 = 5, + refclk_div = 1) + refclk125 = self.platform.request("gtp_refclk") + refclk125_se = Signal() + self.specials += \ + Instance("IBUFDS_GTE2", + i_CEB = 0, + i_I = refclk125.p, + i_IB = refclk125.n, + o_O = refclk125_se) + qpll = QPLL(refclk125_se, qpll_settings) + self.submodules += qpll + self.submodules.ethphy = A7_1000BASEX( + qpll_channel = qpll.channels[0], + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) - def __init__(self, phy="rgmii", **kwargs): - assert phy in ["rgmii", "1000basex"] - BaseSoC.__init__(self, **kwargs) - - # RGMII Ethernet PHY ----------------------------------------------------------------------- - if phy == "rgmii": - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) - - # 1000BaseX Ethernet PHY ------------------------------------------------------------------- - if phy == "1000basex": - # phy - self.comb += self.platform.request("sfp_mgt_clk_sel0", 0).eq(0) - self.comb += self.platform.request("sfp_mgt_clk_sel1", 0).eq(0) - self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(0) - qpll_settings = QPLLSettings( - refclksel = 0b001, - fbdiv = 4, - fbdiv_45 = 5, - refclk_div = 1) - refclk125 = self.platform.request("gtp_refclk") - refclk125_se = Signal() - self.specials += \ - Instance("IBUFDS_GTE2", - i_CEB = 0, - i_I = refclk125.p, - i_IB = refclk125.n, - o_O = refclk125_se) - qpll = QPLL(refclk125_se, qpll_settings) - self.submodules += qpll - self.submodules.ethphy = A7_1000BASEX(qpll.channels[0], self.platform.request("sfp", 0), self.clk_freq) - # timing constraints - self.platform.add_period_constraint(self.ethphy.txoutclk, 1e9/62.5e6) - self.platform.add_period_constraint(self.ethphy.rxoutclk, 1e9/62.5e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.txoutclk, - self.ethphy.rxoutclk) - - # Ethernet MAC ----------------------------------------------------------------------------- - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- def main(): @@ -152,10 +121,9 @@ def main(): help="select Ethernet PHY (rgmii or 1000basex)") args = parser.parse_args() - if args.with_ethernet: - soc = EthernetSoC(args.ethernet_phy, **soc_sdram_argdict(args)) - else: - soc = BaseSoC(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, + ethernet_phy=args.ethernet_phy, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/arty.py b/litex_boards/targets/arty.py index 4157f72..fb5c8c1 100755 --- a/litex_boards/targets/arty.py +++ b/litex_boards/targets/arty.py @@ -19,7 +19,6 @@ from litedram.modules import MT41K128M16 from litedram.phy import s7ddrphy from liteeth.phy.mii import LiteEthPHYMII -from liteeth.mac import LiteEthMAC from liteeth.core import LiteEthUDPIPCore from liteeth.frontend.etherbone import LiteEthEtherbone @@ -53,7 +52,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = arty.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -80,41 +79,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) - + if with_ethernet: + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # EtherboneSoC ------------------------------------------------------------------------------------- @@ -159,10 +130,10 @@ def main(): assert not (args.with_ethernet and args.with_etherbone) cls = BaseSoC if args.with_ethernet: - cls = EthernetSoC + cls = BaseSoC if args.with_etherbone: cls = EtherboneSoC - soc = cls(**soc_sdram_argdict(args)) + soc = cls(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args)) diff --git a/litex_boards/targets/c10lprefkit.py b/litex_boards/targets/c10lprefkit.py index d2518da..29bb1c2 100755 --- a/litex_boards/targets/c10lprefkit.py +++ b/litex_boards/targets/c10lprefkit.py @@ -19,7 +19,6 @@ from litedram.modules import MT48LC16M16 from litedram.phy import GENSDRPHY from liteeth.phy.mii import LiteEthPHYMII -from liteeth.mac import LiteEthMAC from litex.soc.cores.hyperbus import HyperRAM @@ -88,8 +87,7 @@ class BaseSoC(SoCCore): } mem_map.update(SoCCore.mem_map) - - def __init__(self, sys_clk_freq=int(50e6), **kwargs): + def __init__(self, sys_clk_freq=int(50e6), with_ethernet=False, **kwargs): assert sys_clk_freq == int(50e6) platform = c10lprefkit.Platform() @@ -117,41 +115,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, eth_port=0, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_tx.clk, - self.ethphy.crg.cd_eth_rx.clk - ) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -163,8 +133,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/genesys2.py b/litex_boards/targets/genesys2.py index 3a5ada5..3dd903e 100755 --- a/litex_boards/targets/genesys2.py +++ b/litex_boards/targets/genesys2.py @@ -18,7 +18,6 @@ from litedram.modules import MT41J256M16 from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -42,7 +41,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs): platform = genesys2.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -68,40 +67,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -113,8 +85,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/kc705.py b/litex_boards/targets/kc705.py index da933a3..06b28c2 100755 --- a/litex_boards/targets/kc705.py +++ b/litex_boards/targets/kc705.py @@ -20,7 +20,6 @@ from litedram.modules import MT8JTF12864 from litedram.phy import s7ddrphy from liteeth.phy import LiteEthPHY -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -44,7 +43,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs): platform = kc705.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -72,41 +71,14 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHY( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth"), - clk_freq = self.clk_freq) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth"), + clk_freq = self.clk_freq) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -118,8 +90,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/kcu105.py b/litex_boards/targets/kcu105.py index 48d722e..765c5fd 100755 --- a/litex_boards/targets/kcu105.py +++ b/litex_boards/targets/kcu105.py @@ -18,7 +18,6 @@ from litedram.modules import EDY4016A from litedram.phy import usddrphy from liteeth.phy.ku_1000basex import KU_1000BASEX -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -51,7 +50,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(125e6), **kwargs): + def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs): platform = kcu105.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -79,42 +78,15 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, - data_pads = self.platform.request("sfp", 0), - sys_clk_freq = self.clk_freq) - self.add_csr("ethphy") - self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) - self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.cd_eth_rx.clk, - self.ethphy.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) + self.add_csr("ethphy") + self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -126,8 +98,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/mimas_a7.py b/litex_boards/targets/mimas_a7.py index 4859298..3d911df 100755 --- a/litex_boards/targets/mimas_a7.py +++ b/litex_boards/targets/mimas_a7.py @@ -20,7 +20,6 @@ from litedram.modules import MT41J128M16 from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -46,7 +45,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = mimas_a7.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -72,37 +71,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -113,8 +88,8 @@ def main(): vivado_build_args(parser) parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build(**vivado_build_argdict(args)) diff --git a/litex_boards/targets/netv2.py b/litex_boards/targets/netv2.py index 8cfe4f4..817fac0 100755 --- a/litex_boards/targets/netv2.py +++ b/litex_boards/targets/netv2.py @@ -18,7 +18,6 @@ from litedram.modules import K4B2G1646F from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -47,10 +46,10 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = netv2.Platform() - # SoCCore ------------------------------------------------------------------------------_--- + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG -------------------------------------------------------------------------------------- @@ -73,40 +72,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/50e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/50e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -118,8 +90,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/nexys4ddr.py b/litex_boards/targets/nexys4ddr.py index 75a490c..6137f32 100755 --- a/litex_boards/targets/nexys4ddr.py +++ b/litex_boards/targets/nexys4ddr.py @@ -18,7 +18,6 @@ from litedram.modules import MT47H64M16 from litedram.phy import s7ddrphy from liteeth.phy.rmii import LiteEthPHYRMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -46,7 +45,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), **kwargs): + def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, **kwargs): platform = nexys4ddr.Platform() # SoCCore ----------------------------------_----------------------------------------------- @@ -72,40 +71,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -119,8 +91,9 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), + with_ethernet=args.with_ethernet, + **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/nexys_video.py b/litex_boards/targets/nexys_video.py index 6b693da..c62d6a1 100755 --- a/litex_boards/targets/nexys_video.py +++ b/litex_boards/targets/nexys_video.py @@ -18,7 +18,6 @@ from litedram.modules import MT41K256M16 from litedram.phy import s7ddrphy from liteeth.phy.s7rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -46,7 +45,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), **kwargs): + def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs): platform = nexys_video.Platform() # SoCCore ---------------------------------------------------------------------------------- @@ -72,40 +71,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, **kwargs): - BaseSoC.__init__(self, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC( - phy = self.ethphy, - dw = 32, - interface = "wishbone", - endianness = self.cpu.endianness) - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -117,8 +89,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(**soc_sdram_argdict(args)) + soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/simple.py b/litex_boards/targets/simple.py index 7250c98..b7befc8 100755 --- a/litex_boards/targets/simple.py +++ b/litex_boards/targets/simple.py @@ -14,12 +14,11 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.builder import * from liteeth.phy import LiteEthPHY -from liteeth.mac import LiteEthMAC # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, platform, **kwargs): + def __init__(self, platform, with_ethernet=False, **kwargs): sys_clk_freq = int(1e9/platform.default_clk_period) # SoCCore ---------------------------------------------------------------------------------- @@ -28,30 +27,14 @@ class BaseSoC(SoCCore): # CRG -------------------------------------------------------------------------------------- self.submodules.crg = CRG(platform.request(platform.default_clk_name)) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, platform, **kwargs): - BaseSoC.__init__(self, platform, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHY( - clock_pads = self.platform.request("eth_clocks"), - pads = self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") + if with_ethernet: + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth"), + clk_freq = self.clk_freq) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -72,8 +55,7 @@ def main(): platform = platform_module.Platform(toolchain=args.gateware_toolchain) else: platform = platform_module.Platform() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(platform, **soc_core_argdict(args)) + soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder.build() diff --git a/litex_boards/targets/versa_ecp5.py b/litex_boards/targets/versa_ecp5.py index b5be138..9991a81 100755 --- a/litex_boards/targets/versa_ecp5.py +++ b/litex_boards/targets/versa_ecp5.py @@ -22,7 +22,6 @@ from litedram.modules import MT41K64M16 from litedram.phy import ECP5DDRPHY from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII -from liteeth.mac import LiteEthMAC # CRG ---------------------------------------------------------------------------------------------- @@ -73,7 +72,7 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs): + def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs): platform = versa_ecp5.Platform(toolchain=toolchain) # SoCCore -----------------------------------------_---------------------------------------- @@ -100,37 +99,13 @@ class BaseSoC(SoCCore): l2_cache_reverse = True ) -# EthernetSoC -------------------------------------------------------------------------------------- - -class EthernetSoC(BaseSoC): - mem_map = { - "ethmac": 0xb0000000, - } - mem_map.update(BaseSoC.mem_map) - - def __init__(self, toolchain="trellis", **kwargs): - BaseSoC.__init__(self, toolchain=toolchain, **kwargs) - # Ethernet --------------------------------------------------------------------------------- - # phy - self.submodules.ethphy = LiteEthPHYRGMII( - self.platform.request("eth_clocks"), - self.platform.request("eth")) - self.add_csr("ethphy") - # mac - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) - self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") - self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) - self.add_csr("ethmac") - self.add_interrupt("ethmac") - # timing constraints - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) - self.platform.add_false_path_constraints( - self.crg.cd_sys.clk, - self.ethphy.crg.cd_eth_rx.clk, - self.ethphy.crg.cd_eth_tx.clk) + if with_ethernet: + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + self.add_csr("ethphy") + self.add_ethernet(phy=self.ethphy) # Build -------------------------------------------------------------------------------------------- @@ -147,8 +122,7 @@ def main(): help="enable Ethernet support") args = parser.parse_args() - cls = EthernetSoC if args.with_ethernet else BaseSoC - soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args)) + soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args)) builder = Builder(soc, **builder_argdict(args)) builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {} builder.build(**builder_kargs) diff --git a/litex_boards/targets/zcu104.py b/litex_boards/targets/zcu104.py index 5a35687..f1f662f 100755 --- a/litex_boards/targets/zcu104.py +++ b/litex_boards/targets/zcu104.py @@ -51,7 +51,7 @@ class BaseSoC(SoCCore): def __init__(self, sys_clk_freq=int(125e6), **kwargs): platform = zcu104.Platform() - # SoCCore -------------------------------------------------------------------------_-------- + # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs) # CRG --------------------------------------------------------------------------------------