From 5d52bc54612a7c6cf1fd5cd38a7b889b40742cff Mon Sep 17 00:00:00 2001 From: Arusekk Date: Tue, 8 Feb 2022 09:03:53 +0100 Subject: [PATCH] Fix seven_seg pin assignment in DE1-SoC Fixes quartus build error: ``` Error (171016): Can't place node "seven_seg5[6]" -- illegal location assignment PIN_AA2 File: /home/arusekk/src/fpga-proj/build/de1soc/gateware/de1soc.v Line: 49 ``` --- litex_boards/platforms/terasic_de1soc.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/litex_boards/platforms/terasic_de1soc.py b/litex_boards/platforms/terasic_de1soc.py index cdcdad9..19bc987 100644 --- a/litex_boards/platforms/terasic_de1soc.py +++ b/litex_boards/platforms/terasic_de1soc.py @@ -35,7 +35,7 @@ _io = [ ("seven_seg", 2, Pins("AB23 AE29 AD29 AC28 AD30 AC29 AC30"), IOStandard("3.3-V LVTTL")), ("seven_seg", 3, Pins("AD26 AC27 AD25 AC25 AB28 AB25 AB22"), IOStandard("3.3-V LVTTL")), ("seven_seg", 4, Pins("AA24 Y23 Y24 W22 W24 V23 W25"), IOStandard("3.3-V LVTTL")), - ("seven_seg", 5, Pins("V25 AA28 Y27 AB27 AB26 AA26 AA2"), IOStandard("3.3-V LVTTL")), + ("seven_seg", 5, Pins("V25 AA28 Y27 AB27 AB26 AA26 AA25"), IOStandard("3.3-V LVTTL")), # Button ("key", 0, Pins("AA14"), IOStandard("3.3-V LVTTL")),