diff --git a/litex_boards/platforms/terasic_deca.py b/litex_boards/platforms/terasic_deca.py index 74341e5..679f055 100644 --- a/litex_boards/platforms/terasic_deca.py +++ b/litex_boards/platforms/terasic_deca.py @@ -191,7 +191,7 @@ _io = [ Subsignal("tx_data", Pins("U2 W1 N9 W2")), Subsignal("col", Pins("R4")), Subsignal("crs", Pins("P5")), - Subsignal("pcf_en", Pins("V9"), IOStandard("3.3 V")), + Subsignal("pcf_en", Pins("V9"), IOStandard("3.3-V LVTTL")), IOStandard("2.5 V"), ), @@ -306,3 +306,6 @@ class Platform(AlteraPlatform): def do_finalize(self, fragment): AlteraPlatform.do_finalize(self, fragment) self.add_period_constraint(self.lookup_request("clk50", loose=True), 1e9/50e6) + # Generate PLL clocsk in STA + self.toolchain.additional_sdc_commands.append("derive_pll_clocks -create_base_clocks -use_net_name") + self.toolchain.additional_sdc_commands.append("derive_clock_uncertainty") diff --git a/litex_boards/targets/terasic_deca.py b/litex_boards/targets/terasic_deca.py index f81efe2..31cb222 100755 --- a/litex_boards/targets/terasic_deca.py +++ b/litex_boards/targets/terasic_deca.py @@ -18,6 +18,8 @@ from litex.soc.integration.builder import * from litex.soc.cores.video import VideoDVIPHY from litex.soc.cores.led import LedChaser +from liteeth.phy.mii import LiteEthPHYMII + # CRG ---------------------------------------------------------------------------------------------- class _CRG(Module): @@ -51,8 +53,9 @@ class _CRG(Module): # BaseSoC ------------------------------------------------------------------------------------------ class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False, - with_video_terminal=False, + def __init__(self, sys_clk_freq=int(50e6), with_led_chaser=True, with_uartbone=False, with_jtagbone=False, with_video_terminal=False, + with_ethernet=False, with_etherbone=False, eth_ip="192.168.1.50", + eth_dynamic_ip=False, **kwargs): self.platform = platform = deca.Platform() @@ -81,6 +84,23 @@ class BaseSoC(SoCCore): # JTAGbone --------------------------------------------------------------------------------- if with_jtagbone: self.add_jtagbone() + + # Ethernet --------------------------------------------------------------------------------- + if with_ethernet or with_etherbone: + self.platform.toolchain.additional_sdc_commands += [ + 'create_clock -name eth_rx_clk -period 40.0 [get_ports {eth_clocks_rx}]', + 'create_clock -name eth_tx_clk -period 40.0 [get_ports {eth_clocks_tx}]', + 'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_rx_clk}]', + 'set_false_path -from [get_clocks {sys_clk}] -to [get_clocks {eth_tx_clk}]', + 'set_false_path -from [get_clocks {eth_rx_clk}] -to [get_clocks {eth_tx_clk}]', + ] + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) + if with_ethernet: + self.add_ethernet(phy=self.ethphy, dynamic_ip=eth_dynamic_ip) + if with_etherbone: + self.add_etherbone(phy=self.ethphy, ip_address=eth_ip) # Video ------------------------------------------------------------------------------------ if with_video_terminal: @@ -100,6 +120,11 @@ def main(): parser.add_argument("--build", action="store_true", help="Build bitstream.") parser.add_argument("--load", action="store_true", help="Load bitstream.") parser.add_argument("--sys-clk-freq", default=50e6, help="System clock frequency.") + ethopts = parser.add_mutually_exclusive_group() + ethopts.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") + ethopts.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support.") + parser.add_argument("--eth-ip", default="192.168.1.50", type=str, help="Ethernet/Etherbone IP address.") + parser.add_argument("--eth-dynamic-ip", action="store_true", help="Enable dynamic Ethernet IP addresses setting.") parser.add_argument("--with-uartbone", action="store_true", help="Enable UARTbone support.") parser.add_argument("--with-jtagbone", action="store_true", help="Enable JTAGbone support.") parser.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (VGA).") @@ -109,6 +134,10 @@ def main(): soc = BaseSoC( sys_clk_freq = int(float(args.sys_clk_freq)), + with_ethernet = args.with_ethernet, + with_etherbone = args.with_etherbone, + eth_ip = args.eth_ip, + eth_dynamic_ip = args.eth_dynamic_ip, with_uartbone = args.with_uartbone, with_jtagbone = args.with_jtagbone, with_video_terminal = args.with_video_terminal,