diff --git a/litex_boards/platforms/sqrl_acorn_cle_215.py b/litex_boards/platforms/sqrl_acorn.py similarity index 83% rename from litex_boards/platforms/sqrl_acorn_cle_215.py rename to litex_boards/platforms/sqrl_acorn.py index 1ddefd7..5c4596d 100644 --- a/litex_boards/platforms/sqrl_acorn_cle_215.py +++ b/litex_boards/platforms/sqrl_acorn.py @@ -4,8 +4,12 @@ # Copyright (c) 2020 Florent Kermarrec # SPDX-License-Identifier: BSD-2-Clause -# The Acorn CLE 215+ is a cryptocurrency mining accelerator card from SQRL that can be repurposed -# as a generic FPGA PCIe development board: http://www.squirrelsresearch.com/acorn-cle-215-plus +# The Acorn (CLE-101, CLE-215(+)) are cryptocurrency mining accelerator cards from SQRL that can be +# repurposed as generic FPGA PCIe development boards: +# - http://www.squirrelsresearch.com/acorn-cle-101 +# - http://www.squirrelsresearch.com/acorn-cle-215-plus +# The 101 variant is eguivalent to the LiteFury and 215 variant equivalent to the NiteFury from +# RHSResearchLLC that are documented at: https://github.com/RHSResearchLLC/NiteFury-and-LiteFury. from litex.build.generic_platform import * from litex.build.xilinx import XilinxPlatform @@ -14,19 +18,19 @@ from litex.build.openocd import OpenOCD # IOs ---------------------------------------------------------------------------------------------- _io = [ - # Clk / Rst + # Clk / Rst. ("clk200", 0, Subsignal("p", Pins("J19"), IOStandard("DIFF_SSTL15")), Subsignal("n", Pins("H19"), IOStandard("DIFF_SSTL15")) ), - # Leds + # Leds. ("user_led", 0, Pins("G3"), IOStandard("LVCMOS33")), ("user_led", 1, Pins("H3"), IOStandard("LVCMOS33")), ("user_led", 2, Pins("G4"), IOStandard("LVCMOS33")), ("user_led", 3, Pins("H4"), IOStandard("LVCMOS33")), - # SPIFlash + # SPIFlash. ("spiflash", 0, Subsignal("cs_n", Pins("T19")), Subsignal("mosi", Pins("P22")), @@ -36,7 +40,7 @@ _io = [ IOStandard("LVCMOS33") ), - # PCIe + # PCIe. ("pcie_clkreq_n", 0, Pins("G1"), IOStandard("LVCMOS33")), ("pcie_x4", 0, Subsignal("rst_n", Pins("J1"), IOStandard("LVCMOS33"), Misc("PULLUP=TRUE")), @@ -48,7 +52,7 @@ _io = [ Subsignal("tx_n", Pins("A6 A4 C5 C7")), ), - # DDR3 SDRAM + # DDR3 SDRAM. ("ddram", 0, Subsignal("a", Pins( "M15 L21 M16 L18 K21 M18 M21 N20", @@ -77,7 +81,7 @@ _io = [ ] _serial_io = [ - # Serial adapter on P2 + # Serial adapter on P2. ("serial", 0, Subsignal("tx", Pins("K2")), Subsignal("rx", Pins("J2")), @@ -87,7 +91,7 @@ _serial_io = [ ] _sdcard_io = [ - # SPI SDCard adapter on P2 + # SPI SDCard adapter on P2. # https://spoolqueue.com/new-design/fpga/migen/litex/2020/08/11/acorn-cle-215.html ("spisdcard", 0, Subsignal("clk", Pins("J2")), @@ -105,8 +109,14 @@ class Platform(XilinxPlatform): default_clk_name = "clk200" default_clk_period = 1e9/200e6 - def __init__(self): - XilinxPlatform.__init__(self, "xc7a200t-fbg484-2", _io, toolchain="vivado") + def __init__(self, variant="cle-215+"): + device = { + "cle-101": "xc7a100t-fgg484-2", + "cle-215": "xc7a200t-fbg484-2", + "cle-215+": "xc7a200t-fbg484-3" + }[variant] + + XilinxPlatform.__init__(self, device, _io, toolchain="vivado") self.add_extension(_serial_io) self.add_extension(_sdcard_io) self.add_platform_command("set_property INTERNAL_VREF 0.750 [get_iobanks 34]") diff --git a/litex_boards/targets/sqrl_acorn_cle_215.py b/litex_boards/targets/sqrl_acorn.py similarity index 93% rename from litex_boards/targets/sqrl_acorn_cle_215.py rename to litex_boards/targets/sqrl_acorn.py index 83f6c20..dbe32d5 100755 --- a/litex_boards/targets/sqrl_acorn_cle_215.py +++ b/litex_boards/targets/sqrl_acorn.py @@ -8,7 +8,7 @@ # Build/Use ---------------------------------------------------------------------------------------- # Build/Load bitstream: -# ./acorn_cle_215.py --uart-name=crossover --with-pcie --build --driver --load (or --flash) +# ./acorn_cle.py --uart-name=crossover --with-pcie --build --driver --load (or --flash) # #.Build the kernel and load it: # cd build//driver/kernel @@ -29,7 +29,7 @@ import sys from migen import * -from litex_boards.platforms import acorn_cle_215 +from litex_boards.platforms import acorn from litex.soc.interconnect.csr import * from litex.soc.integration.soc_core import * @@ -72,12 +72,12 @@ class CRG(Module): # BaseSoC ----------------------------------------------------------------------------------------- class BaseSoC(SoCCore): - def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, **kwargs): - platform = acorn_cle_215.Platform() + def __init__(self, variant="cle-215+", sys_clk_freq=int(100e6), with_pcie=False, with_sata=False, **kwargs): + platform = acorn.Platform(variant=variant) # SoCCore ---------------------------------------------------------------------------------- SoCCore.__init__(self, platform, sys_clk_freq, - ident = "LiteX SoC on Acorn CLE 215+", + ident = "LiteX SoC on Acorn CLE-101/215(+)", ident_version = True, **kwargs) @@ -155,10 +155,11 @@ class BaseSoC(SoCCore): # Build -------------------------------------------------------------------------------------------- def main(): - parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE 215+") + parser = argparse.ArgumentParser(description="LiteX SoC on Acorn CLE-101/215(+)") parser.add_argument("--build", action="store_true", help="Build bitstream") parser.add_argument("--load", action="store_true", help="Load bitstream") parser.add_argument("--flash", action="store_true", help="Flash bitstream") + parser.add_argument("--variant", default="cle-215+", help="Board variant: cle-215+ (default), cle-215 or cle-101") parser.add_argument("--sys-clk-freq", default=100e6, help="System clock frequency (default: 100MHz)") pcieopts = parser.add_mutually_exclusive_group() pcieopts.add_argument("--with-pcie", action="store_true", help="Enable PCIe support") @@ -170,6 +171,7 @@ def main(): args = parser.parse_args() soc = BaseSoC( + variant = args.variant, sys_clk_freq = int(float(args.sys_clk_freq)), with_pcie = args.with_pcie, with_sata = args.with_sata,